[PATCH v2 0/2] mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support

[nick . hawkins]

From: Nick Hawkins <nick.hawkins@xxxxxxx>

The HPE GSC is an ARM64 (Cortex-A53) BMC SoC used on HPE ProLiant
servers.  Its eMMC controller is based on the DesignWare Cores MSHC IP
(snps,dwcmshc) but requires a small set of platform-specific quirks
that cannot be expressed through the existing generic dwcmshc code
paths.

This series adds support for the 'hpe,gsc-dwcmshc' compatible:

Patch 1 extends the snps,dwcmshc-sdhci.yaml binding to document the
new compatible and the mandatory 'hpe,gxp-sysreg' syscon phandle for
MSHCCS register access.  The HPE GSC exposes only a single 'core'
clock, so the clocks/clock-names properties are constrained to
maxItems: 1 for this compatible.

Patch 2 adds the HPE-specific driver code in sdhci-of-dwcmshc.c:

  * dwcmshc_hpe_set_clock(): SDHCI_CLOCK_CONTROL.freq_sel is wired to
    a clock mux on the GSC SoC, not a divider.  When running at
    200 MHz (HS200) freq_sel must be forced to 1 to select the correct
    high-frequency source.

  * dwcmshc_hpe_vendor_specific(): disables the command-conflict check
    and programs ATCTRL = 0x021f0005 for reliable HS200 signal integrity
    on the GSC board topology (auto-tuning enable, centre-phase mode,
    tune-clock-stop, pre/post-change delays = 3).

  * dwcmshc_hpe_reset(): calls sdhci_reset(), re-applies vendor config,
    and unconditionally re-sets CARD_IS_EMMC.  The controller clears this
    bit on every reset; leaving it clear causes card-detect
    misidentification on the eMMC-only slot.

  * dwcmshc_hpe_set_uhs_signaling(): mirrors upstream
    dwcmshc_set_uhs_signaling() but always asserts CARD_IS_EMMC.

  * dwcmshc_hpe_gsc_init(): obtains the SoC register block via the
    'hpe,gxp-sysreg' syscon phandle and sets SCGSyncDis (BIT(18)) in
    MSHCCS (offset 0x110) to allow the HS200 RX delay lines to settle
    while the card clock is stopped.  Enables SDHCI v4 mode.

  * sdhci_dwcmshc_hpe_gsc_pdata sets SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
    (base clock not in capabilities) and SDHCI_QUIRK2_PRESET_VALUE_BROKEN
    (preset-value registers not populated in GSC ROM).

All new symbols are exclusively selected by the 'hpe,gsc-dwcmshc' OF
match entry.  No existing platform (Rockchip, T-Head, sg2042, Sophgo,
etc.) has any code path change.

Note: the DTS node for 'hpe,gsc-dwcmshc' will be submitted separately
as part of the HPE GSC base platform series (arch/arm64/boot/dts/hpe/).

Changes since v1:
  - Replaced the second reg entry for MSHCCS with an 'hpe,gxp-sysreg'
    syscon phandle + regmap access, as suggested by Conor Dooley.
  - Driver now uses syscon_regmap_lookup_by_phandle() and
    regmap_update_bits() instead of devm_platform_ioremap_resource().

Nick Hawkins (2):
  dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible
  mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support

 .../bindings/mmc/snps,dwcmshc-sdhci.yaml      |  38 ++++
 drivers/mmc/host/sdhci-of-dwcmshc.c           | 173 ++++++++++++++++++
 2 files changed, 211 insertions(+)

-- 
2.34.1