Re: [PATCH v2 4/5] media: iris: Add platform data for X1P42100

[Dmitry Baryshkov]

On Mon, Mar 09, 2026 at 11:49:42AM +0100, Krzysztof Kozlowski wrote:
> On 09/03/2026 11:43, Konrad Dybcio wrote:
> > On 3/7/26 2:18 PM, Krzysztof Kozlowski wrote:
> >> On Fri, Mar 06, 2026 at 04:44:32PM +0800, Wangao Wang wrote:
> >>> Introduce platform data for X1P42100, derived from SM8550 but using a
> >>> different clock configuration and a dedicated OPP setup.
> >>>
> >>> Signed-off-by: Wangao Wang <wangao.wang@xxxxxxxxxxxxxxxx>
> >>> ---
> > 
> > [...]
> > 
> >>> +static const struct platform_clk_data x1p42100_clk_table[] = {
> >>> +	{IRIS_AXI_CLK,		"iface"			},
> >>> +	{IRIS_CTRL_CLK,		"core"			},
> >>> +	{IRIS_HW_CLK,		"vcodec0_core"		},
> >>> +	{IRIS_BSE_HW_CLK,	"vcodec0_bse"		},
> >>
> >> And maybe that's just IRIS_AXI_CLK clock?
> >>
> >> People keep sending downstream code and name such stuff because they
> >> found it in downstream, so I have doubts.
> > 
> > As the dt-bindings commit message states, Iris on Purwa has some new
> > IP that needs its own clock for operation
> 
> 
> It's v3 IPU, yes? So why that block disappeared from further versions? I
> would assume it is still there and the naming just might have changed.
> 
> How this clock is used here looks exactly how v3.5 sequence is done.
> Alternatively that's AXI1 clock?

Looking at Iris docs for Hamoa, Purwa and SM8750, no, BSE is not the
AXI1 clock. It is documented as a separate async clock, it's propagation
is enabled separately, etc.

> 
> Or commit msg should really explain why usage of this clock is different
> than v3.5 uses its clocks.


-- 
With best wishes
Dmitry