Re: [PATCH 0/5] DSI byte clock setting fixup

[Bjorn Andersson]

On Wed, 04 Mar 2026 14:48:26 +0100, Konrad Dybcio wrote:
> There's a conflict between the byte and byte_intf_div2 clocks trying to
> set_rate on their common parent. The latter should follow the rate of
> the former in one way or another anyway, so the fix here is to prevent
> the latter from ratesetting the upstream PLL.
> 
> This series does just that.
> 
> [...]

Applied, thanks!

[1/5] clk: qcom: dispcc-glymur: Fix DSI byte clock rate setting
      commit: 98ea9eda030587601db56425efcd32263d853591
[2/5] clk: qcom: dispcc-kaanapali: Fix DSI byte clock rate setting
      commit: e892f4e3f3d558ce5d7595dca7cce2bd170a19fa
[3/5] clk: qcom: dispcc-milos: Fix DSI byte clock rate setting
      commit: dd5b76257b4048151006620c9895e2f5f0d997eb
[4/5] clk: qcom: dispcc-sm4450: Fix DSI byte clock rate setting
      commit: 7bc48fcdf9e77bf68ef04af015d50df2a9acac00
[5/5] clk: qcom: dispcc[01]-sa8775p: Fix DSI byte clock rate setting
      commit: 2851b6c6a42e22c243aa4cd606a49e2b9acfb6d6

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>