Re: [PATCH 0/7] clk: qcom: sc8180x: PM-related fixes

[Konrad Dybcio]

On 3/9/26 2:00 AM, Val Packett wrote:
> This series mostly ports the fixes that were made over the years to the
> sc8280xp drivers to the sc8180x ones. (With apologies to everyone for
> somewhat stealing the commit messages in places :D)

imitation is the sincerest form of flattery!

> The most pressing issue this resolves is s2idle exit on the Surface Pro X
> being slow and breaking NVMe:
> 
>     nvme 0002:01:00.0: Unable to change power state from D3cold to D0, device inaccessible
>     xhci-hcd xhci-hcd.0.auto: xHC error in resume, USBSTS 0x401, Reinit
>     usb usb1: root hub lost power or was reset
>     usb usb2: root hub lost power or was reset
>     nvme nvme0: controller is down; will reset: CSTS=0xffffffff, PCI_STATUS read failed (134)
>     nvme nvme0: Does your device have a faulty power saving mode enabled?
>     nvme nvme0: Try "nvme_core.default_ps_max_latency_us=0 pcie_aspm=off pcie_port_pm=off" and report a bug
>     nvme 0002:01:00.0: Unable to change power state from D3cold to D0, device inaccessible
> 
> Hopefully it also contributes towards improving power usage eventually..
> 
> One thing I'm left wondering about is 8d114b94fc39 ("clk: qcom:
> gcc-sc8280xp: use collapse-voting for PCIe GDSCs"), not sure if it
> applies and if it does, where I'd find the values. (Downstream dtsi for
> sdmshrike, which is the closest SoC that the msm kernel supports AFAIK,
> was my only reference and it doesn't seem to have anything related.)

No such thing on this platform

> And 9410fb940114 ("clk: qcom: gcc-sc8280xp: use phy-mux clock for PCIe")
> .. we don't have the _src clocks for PCIe defined at all here (o.0)

It'll take some time before they become useful I think, but if you'd like
to add them and boot-test (absolute addresses):

pcie0 0x16b028
pcie1 0x18d028
pcie2 0x19d028
pcie3 0x1a3028

usb_pri 0x10f05c
usb_sec 0x11005c

(all are phymux-like)

Konrad