[PATCH 0/5] watchdog: rzn1: Add support for direct hardware reset

[Herve Codina (Schneider Electric)]

Hi,

The current watchdog driver handling wachdogs of the RZ/N1 SoCs is based
on interrupt only to perform the reset. On the watchdog timeout, an
interrupt is triggered and the software initiates the reset.

The watchdogs available in the RZ/N1 SoCs can directly perform an
hardware reset using their dedicated reset line.

On timeout, the watchdog also asserts its dedicated reset line. This
reset line is connected to the reset controller (part of sysctrl) and,
if this line is enabled as a possible reset source at the reset
controller level, it initiates a system reset.

This series adds support for this feature allowing watchdogs to directly
reset the system with any software needs when a watchdog timeout occurs.

The first two patches are minor fixes and improvements without changing
the current functional behavior.

Patches 3 to 5 add support for the feature adding:
  - The reset line description in the RZ/N1 watchdog binding,
  - A new helper at sysctrl level (sysctrl is handled by the clock
    driver in RZ/N1) to enable watchdog reset sources,
  - The support itself in the watchdog driver putting everything together.

Best regards,
Hervé

Herve Codina (Schneider Electric) (5):
  watchdog: rzn1: Fix reverse xmas tree declaration
  watchdog: rzn1: Use dev_err_probe()
  dt-bindings: watchdog: renesas,rzn1-wdt: Document the reset line
  clk: renesas: r9a06g032: Introduce a helper to set rsten register
  watchdog: rzn1: Add support for direct hardware reset

 .../bindings/watchdog/renesas,rzn1-wdt.yaml   | 22 +++++++
 drivers/clk/renesas/r9a06g032-clocks.c        | 32 ++++++++++
 drivers/watchdog/rzn1_wdt.c                   | 63 ++++++++++++++-----
 .../dt-bindings/watchdog/renesas,rzn1-wdt.h   | 16 +++++
 include/linux/soc/renesas/r9a06g032-sysctrl.h | 12 ++++
 5 files changed, 131 insertions(+), 14 deletions(-)
 create mode 100644 include/dt-bindings/watchdog/renesas,rzn1-wdt.h

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2.53.0