Re: [PATCH] ASoC: codecs: cs42l84: set up PLL for more sample rates

[Mark Brown]

On Sat, Mar 07, 2026 at 10:44:18AM +1000, James Calligeros wrote:

> Fill out more PLL config parameters in the PLL config lookup
> table, and advertise the corresponding sample rates to userspace.
> This enables 44.1, 88.2, 176.4 and 192 kHz output and input.

>  static const struct cs42l84_pll_params pll_ratio_table[] = {
> +	{  2822400, 1, 0, 0x40, 0x000000, 0x03, 0x10, 11289600},
>  	{  3072000, 1, 0, 0x40, 0x000000, 0x03, 0x10, 12288000},
> +	{  5644800, 1, 0, 0x40, 0x000000, 0x03, 0x10, 11289600},
>  	{  6144000, 1, 1, 0x40, 0x000000, 0x03, 0x10, 12288000},
> +	{ 11289600, 0, 0, 0, 0, 0, 0,                 11289600},
>  	{ 12288000, 0, 0, 0, 0, 0, 0,                 12288000},
>  	{ 24576000, 1, 3, 0x40, 0x000000, 0x03, 0x10, 12288000},
>  };

These are adding 44.1kHz based rates with a new value for MCLK (the
final value in each entry).  Those values are read with a switch
statement in cs42l84_pll_config but that only has an entry for 24.576MHz
for some reason, that won't match 112.896MHz and will just leave the
pll_mclk_f with whatever value it had before.  Don't we need a new case
statement there for the new MCLK?

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