Re: [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling

[Aaron Kling]

On Thu, Feb 19, 2026 at 10:07 PM Aaron Kling via B4 Relay
<devnull+webgeek1234.gmail.com@xxxxxxxxxx> wrote:
>
> Add the OSM L3 controller node then add the necessary interconnect
> properties with the appropriate OPP table for each CPU cluster to
> allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
> cluster operating point.
>
> Signed-off-by: Aaron Kling <webgeek1234@xxxxxxxxx>
> ---
> Changes in v3:
> - Squash the last two patches
> - Link to v2: https://lore.kernel.org/r/20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@xxxxxxxxx
>
> Changes in v2:
> - Squash first two patches
> - Update opp tables in last patch to match how the downstream driver
>   parses those tables
> - Link to v1: https://lore.kernel.org/r/20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@xxxxxxxxx
>
> ---
> Aaron Kling (2):
>       dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
>       arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
>
>  .../bindings/interconnect/qcom,osm-l3.yaml         |   1 +
>  arch/arm64/boot/dts/qcom/sm8550.dtsi               | 367 +++++++++++++++++++++
>  2 files changed, 368 insertions(+)
> ---
> base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
> change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207
>
> Best regards,
> --
> Aaron Kling <webgeek1234@xxxxxxxxx>

What is the normal merge sequence and window for linux-arm-msm? I see
several things that have been picked up for -next recently, but none
of my sm8550 patches that have been reviewed / approved have been
picked up yet.

Sincerely,
Aaron