[PATCH v2 3/3] gpu: nova-core: use DeviceSize trait for u64 size constants
From: John Hubbard
Date: Wed Mar 11 2026 - 23:15:46 EST
Replace manual usize-to-u64 conversions of SZ_* constants with the
DeviceSize trait's associated constants on u64. With the DeviceSize
trait in scope, u64::SZ_1M replaces usize_as_u64(SZ_1M) and similar.
Also switch Alignment::new::<SZ_*>() calls to Alignment::from_u64(),
which accepts u64 DeviceSize constants directly.
This removes several now-unused imports: usize_as_u64 and the SZ_*
type-level constants.
Signed-off-by: John Hubbard <jhubbard@xxxxxxxxxx>
---
drivers/gpu/nova-core/fb.rs | 31 ++++++++++++++-----------------
drivers/gpu/nova-core/gsp/fw.rs | 18 +++++++-----------
drivers/gpu/nova-core/regs.rs | 6 +++---
3 files changed, 24 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs
index 6536d0035cb1..aa80fffc4a30 100644
--- a/drivers/gpu/nova-core/fb.rs
+++ b/drivers/gpu/nova-core/fb.rs
@@ -13,7 +13,7 @@
Alignable,
Alignment, //
},
- sizes::*,
+ sizes::DeviceSize,
sync::aref::ARef, //
};
@@ -23,10 +23,7 @@
firmware::gsp::GspFirmware,
gpu::Chipset,
gsp,
- num::{
- usize_as_u64,
- FromSafeCast, //
- },
+ num::FromSafeCast,
regs,
};
@@ -126,8 +123,8 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
if f.alternate() {
let size = self.len();
- if size < usize_as_u64(SZ_1M) {
- let size_kib = size / usize_as_u64(SZ_1K);
+ if size < u64::SZ_1M {
+ let size_kib = size / u64::SZ_1K;
f.write_fmt(fmt!(
"{:#x}..{:#x} ({} KiB)",
self.0.start,
@@ -135,7 +132,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
size_kib
))
} else {
- let size_mib = size / usize_as_u64(SZ_1M);
+ let size_mib = size / u64::SZ_1M;
f.write_fmt(fmt!(
"{:#x}..{:#x} ({} MiB)",
self.0.start,
@@ -185,14 +182,14 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw: &GspFirmware) -> Result<
let vga_workspace = {
let vga_base = {
- const NV_PRAMIN_SIZE: u64 = usize_as_u64(SZ_1M);
+ const NV_PRAMIN_SIZE: u64 = u64::SZ_1M;
let base = fb.end - NV_PRAMIN_SIZE;
if hal.supports_display(bar) {
match regs::NV_PDISP_VGA_WORKSPACE_BASE::read(bar).vga_workspace_addr() {
Some(addr) => {
if addr < base {
- const VBIOS_WORKSPACE_SIZE: u64 = usize_as_u64(SZ_128K);
+ const VBIOS_WORKSPACE_SIZE: u64 = u64::SZ_128K;
// Point workspace address to end of framebuffer.
fb.end - VBIOS_WORKSPACE_SIZE
@@ -211,15 +208,15 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw: &GspFirmware) -> Result<
};
let frts = {
- const FRTS_DOWN_ALIGN: Alignment = Alignment::new::<SZ_128K>();
- const FRTS_SIZE: u64 = usize_as_u64(SZ_1M);
+ const FRTS_DOWN_ALIGN: Alignment = Alignment::from_u64(u64::SZ_128K);
+ const FRTS_SIZE: u64 = u64::SZ_1M;
let frts_base = vga_workspace.start.align_down(FRTS_DOWN_ALIGN) - FRTS_SIZE;
FbRange(frts_base..frts_base + FRTS_SIZE)
};
let boot = {
- const BOOTLOADER_DOWN_ALIGN: Alignment = Alignment::new::<SZ_4K>();
+ const BOOTLOADER_DOWN_ALIGN: Alignment = Alignment::from_u64(u64::SZ_4K);
let bootloader_size = u64::from_safe_cast(gsp_fw.bootloader.ucode.size());
let bootloader_base = (frts.start - bootloader_size).align_down(BOOTLOADER_DOWN_ALIGN);
@@ -227,7 +224,7 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw: &GspFirmware) -> Result<
};
let elf = {
- const ELF_DOWN_ALIGN: Alignment = Alignment::new::<SZ_64K>();
+ const ELF_DOWN_ALIGN: Alignment = Alignment::from_u64(u64::SZ_64K);
let elf_size = u64::from_safe_cast(gsp_fw.size);
let elf_addr = (boot.start - elf_size).align_down(ELF_DOWN_ALIGN);
@@ -235,7 +232,7 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw: &GspFirmware) -> Result<
};
let wpr2_heap = {
- const WPR2_HEAP_DOWN_ALIGN: Alignment = Alignment::new::<SZ_1M>();
+ const WPR2_HEAP_DOWN_ALIGN: Alignment = Alignment::from_u64(u64::SZ_1M);
let wpr2_heap_size =
gsp::LibosParams::from_chipset(chipset).wpr_heap_size(chipset, fb.end);
let wpr2_heap_addr = (elf.start - wpr2_heap_size).align_down(WPR2_HEAP_DOWN_ALIGN);
@@ -244,7 +241,7 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw: &GspFirmware) -> Result<
};
let wpr2 = {
- const WPR2_DOWN_ALIGN: Alignment = Alignment::new::<SZ_1M>();
+ const WPR2_DOWN_ALIGN: Alignment = Alignment::from_u64(u64::SZ_1M);
let wpr2_addr = (wpr2_heap.start - u64::from_safe_cast(size_of::<gsp::GspFwWprMeta>()))
.align_down(WPR2_DOWN_ALIGN);
@@ -252,7 +249,7 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw: &GspFirmware) -> Result<
};
let heap = {
- const HEAP_SIZE: u64 = usize_as_u64(SZ_1M);
+ const HEAP_SIZE: u64 = u64::SZ_1M;
FbRange(wpr2.start - HEAP_SIZE..wpr2.start)
};
diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw.rs
index 25fca1f6db2c..454a4a92105a 100644
--- a/drivers/gpu/nova-core/gsp/fw.rs
+++ b/drivers/gpu/nova-core/gsp/fw.rs
@@ -15,10 +15,7 @@
Alignable,
Alignment, //
},
- sizes::{
- SZ_128K,
- SZ_1M, //
- },
+ sizes::DeviceSize,
transmute::{
AsBytes,
FromBytes, //
@@ -69,7 +66,7 @@ fn client_alloc_size() -> u64 {
/// Returns the amount of memory to reserve for management purposes for a framebuffer of size
/// `fb_size`.
fn management_overhead(fb_size: u64) -> u64 {
- let fb_size_gb = fb_size.div_ceil(u64::from_safe_cast(kernel::sizes::SZ_1G));
+ let fb_size_gb = fb_size.div_ceil(u64::SZ_1G);
u64::from(bindings::GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB)
.saturating_mul(fb_size_gb)
@@ -91,9 +88,8 @@ impl LibosParams {
const LIBOS2: LibosParams = LibosParams {
carveout_size: num::u32_as_u64(bindings::GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2),
allowed_heap_size: num::u32_as_u64(bindings::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB)
- * num::usize_as_u64(SZ_1M)
- ..num::u32_as_u64(bindings::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB)
- * num::usize_as_u64(SZ_1M),
+ * u64::SZ_1M
+ ..num::u32_as_u64(bindings::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB) * u64::SZ_1M,
};
/// Version 3 of the GSP LIBOS (GA102+)
@@ -101,9 +97,9 @@ impl LibosParams {
carveout_size: num::u32_as_u64(bindings::GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL),
allowed_heap_size: num::u32_as_u64(
bindings::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB,
- ) * num::usize_as_u64(SZ_1M)
+ ) * u64::SZ_1M
..num::u32_as_u64(bindings::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB)
- * num::usize_as_u64(SZ_1M),
+ * u64::SZ_1M,
};
/// Returns the libos parameters corresponding to `chipset`.
@@ -181,7 +177,7 @@ pub(crate) fn new(gsp_firmware: &GspFirmware, fb_layout: &FbLayout) -> Self {
gspFwWprEnd: fb_layout
.vga_workspace
.start
- .align_down(Alignment::new::<SZ_128K>()),
+ .align_down(Alignment::from_u64(u64::SZ_128K)),
gspFwHeapVfPartitionCount: fb_layout.vf_partition_count,
fbSize: fb_layout.fb.end - fb_layout.fb.start,
vgaWorkspaceOffset: fb_layout.vga_workspace.start,
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 53f412f0ca32..8514b4bd7279 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -9,6 +9,7 @@
use kernel::{
prelude::*,
+ sizes::DeviceSize,
time, //
};
@@ -32,7 +33,6 @@
Architecture,
Chipset, //
},
- num::FromSafeCast,
};
// PMC
@@ -129,7 +129,7 @@ impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE {
/// Returns the usable framebuffer size, in bytes.
pub(crate) fn usable_fb_size(self) -> u64 {
let size = (u64::from(self.lower_mag()) << u64::from(self.lower_scale()))
- * u64::from_safe_cast(kernel::sizes::SZ_1M);
+ * u64::SZ_1M;
if self.ecc_mode_enabled() {
// Remove the amount of memory reserved for ECC (one per 16 units).
@@ -218,7 +218,7 @@ pub(crate) fn completed(self) -> bool {
impl NV_USABLE_FB_SIZE_IN_MB {
/// Returns the usable framebuffer size, in bytes.
pub(crate) fn usable_fb_size(self) -> u64 {
- u64::from(self.value()) * u64::from_safe_cast(kernel::sizes::SZ_1M)
+ u64::from(self.value()) * u64::SZ_1M
}
}
--
2.53.0