[PATCH 0/2] Add PCIe clocks and reset for R9A09G056 and R9A09G057 SoCs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Hi all,

This patch series adds the necessary PCIe clocks and reset for the
R9A09G056 and R9A09G057 SoCs. This is essential for enabling PCIe
functionality on these platforms.

Note, there are checkpatch warnings about `Alignment should match
open parenthesis` in the `DEF_MOD` and `DEF_RST` macros. These are
intentional to maintain readability and consistency with existing
code style in the driver.

Cheers,
Prabhakar

Lad Prabhakar (2):
  clk: renesas: r9a09g056: Add PCIe clocks and reset
  clk: renesas: r9a09g057: Add PCIe clocks and reset

 drivers/clk/renesas/r9a09g056-cpg.c | 5 +++++
 drivers/clk/renesas/r9a09g057-cpg.c | 5 +++++
 2 files changed, 10 insertions(+)

-- 
2.53.0