[PATCH 1/2] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add PHY interrupt support
From: Prabhakar
Date: Thu Mar 12 2026 - 12:13:05 EST
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Add interrupt support for the GMAC1 and GMAC2 PHYs on the RZ/N2H EVK
board. The PHYs are connected to the ICU via IRQ14 and IRQ15 lines
respectively.
Define RZN2H_IRQxx macros in the SoC DTSI to map the ICU IRQ_NS lines
to their absolute ICU interrupt space offsets.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 18 ++++++++++++++++++
.../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 9 +++++++--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 6218cef2fca5..f697e9698ed3 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -8,6 +8,24 @@
#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */
+#define RZN2H_IRQ0 16
+#define RZN2H_IRQ1 17
+#define RZN2H_IRQ2 18
+#define RZN2H_IRQ3 19
+#define RZN2H_IRQ4 20
+#define RZN2H_IRQ5 21
+#define RZN2H_IRQ6 22
+#define RZN2H_IRQ7 23
+#define RZN2H_IRQ8 24
+#define RZN2H_IRQ9 25
+#define RZN2H_IRQ10 26
+#define RZN2H_IRQ11 27
+#define RZN2H_IRQ12 28
+#define RZN2H_IRQ13 29
+#define RZN2H_IRQ14 30
+#define RZN2H_IRQ15 31
+
/ {
compatible = "renesas,r9a09g087";
#address-cells = <2>;
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index 19f0a2c06753..821a74edab50 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -303,6 +303,7 @@ &i2c1 {
};
&mdio1_phy {
+ interrupts-extended = <&icu RZN2H_IRQ15 IRQ_TYPE_EDGE_FALLING>;
/*
* PHY3 Reset Configuration:
*
@@ -312,6 +313,7 @@ &mdio1_phy {
};
&mdio2_phy {
+ interrupts-extended = <&icu RZN2H_IRQ14 IRQ_TYPE_EDGE_FALLING>;
/*
* PHY2 Reset Configuration:
*
@@ -338,6 +340,7 @@ can1_pins: can1-pins {
* DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
* DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7,
* P31_2, P31_4 and P31_5 are used for Ethernet port 2
+ * DSW13[7] OFF; DSW13[8] ON - use pin P13_7 for IRQ14
*/
gmac2_pins: gmac2-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
@@ -358,7 +361,8 @@ gmac2_pins: gmac2-pins {
<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
- <RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
+ <RZT2H_PORT_PINMUX(31, 0, 0x2)>, /* ETH2_REFCLK */
+ <RZT2H_PORT_PINMUX(13, 7, 0x0)>; /* IRQ14 */
};
@@ -388,7 +392,8 @@ gmac1_pins: gmac1-pins {
<RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
- <RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
+ <RZT2H_PORT_PINMUX(34, 6, 0x2)>, /* ETH3_REFCLK */
+ <RZT2H_PORT_PINMUX(17, 3, 0x0)>; /* IRQ15 */
};
/*
--
2.53.0