Re: [PATCH v3 1/7] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding

[Dmitry Baryshkov]

On Fri, Mar 13, 2026 at 06:49:35PM +0530, Vikash Garodia wrote:
> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
> compared to previous generation, iris3x, it has,
> - separate power domains for stream and pixel processing hardware blocks
>   (bse and vpp).
> - additional power domain for apv codec.
> - power domains for individual pipes (VPPx).
> - different clocks and reset lines.
> 
> This patch depends on
> https://github.com/devicetree-org/dt-schema/pull/184/changes/d341298d62805bc972dfba691da6b3b62aa3ff15
> 
> Nacked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>
> Signed-off-by: Vikash Garodia <vikash.garodia@xxxxxxxxxxxxxxxx>
> ---
>  .../bindings/media/qcom,kaanapali-iris.yaml        | 254 +++++++++++++++++++++
>  include/dt-bindings/media/qcom,kaanapali-iris.h    |  18 ++
>  2 files changed, 272 insertions(+)

> +
> +    video-codec@2000000 {
> +        compatible = "qcom,kaanapali-iris";
> +        reg = <0x02000000 0xf0000>;
> +
> +        clocks = <&gcc_video_axi0_clk>,
> +                 <&video_cc_mvs0c_clk>,
> +                 <&video_cc_mvs0_clk>,
> +                 <&gcc_video_axi1_clk>,
> +                 <&video_cc_mvs0c_freerun_clk>,
> +                 <&video_cc_mvs0_freerun_clk>,
> +                 <&video_cc_mvs0b_clk>,
> +                 <&video_cc_mvs0_vpp0_clk>,
> +                 <&video_cc_mvs0_vpp1_clk>,
> +                 <&video_cc_mvs0a_clk>;
> +        clock-names = "iface",
> +                      "core",
> +                      "vcodec0_core",
> +                      "iface1",
> +                      "core_freerun",
> +                      "vcodec0_core_freerun",
> +                      "vcodec_bse",
> +                      "vcodec_vpp0",
> +                      "vcodec_vpp1",
> +                      "vcodec_apv";
> +
> +        dma-coherent;
> +
> +        interconnects = <&gem_noc_master_appss_proc &config_noc_slave_venus_cfg>,
> +                        <&mmss_noc_master_video_mvp &mc_virt_slave_ebi1>;
> +        interconnect-names = "cpu-cfg",
> +                             "video-mem";
> +
> +        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +
> +        iommu-map = <IRIS_BITSTREAM &apps_smmu 0x1944 0x0 0x1>,
> +                    <IRIS_NON_PIXEL &apps_smmu 0x1940 0x0 0x1>,
> +                    <IRIS_NON_PIXEL &apps_smmu 0x1a20 0x0 0x1>,

It think we still haven't settled on letting iommu-map to have several
entries for a single function.

> +                    <IRIS_PIXEL &apps_smmu 0x1943 0x0 0x1>,
> +                    <IRIS_SECURE_BITSTREAM &apps_smmu 0x1946 0x0 0x1>,
> +                    <IRIS_SECURE_NON_PIXEL &apps_smmu 0x1941 0x0 0x1>,
> +                    <IRIS_SECURE_NON_PIXEL &apps_smmu 0x1a21 0x0 0x1>,
> +                    <IRIS_SECURE_PIXEL &apps_smmu 0x1945 0x0 0x1>,
> +                    <IRIS_FIRMWARE &apps_smmu 0x1a22 0x0 0x1>;
> +
> +        memory-region = <&video_mem>;
> +
> +        operating-points-v2 = <&iris_opp_table>;
> +
> +        power-domains = <&video_cc_mvs0c_gdsc>,
> +                        <&video_cc_mvs0_gdsc>,
> +                        <&rpmhpd RPMHPD_MXC>,
> +                        <&rpmhpd RPMHPD_MMCX>,
> +                        <&video_cc_mvs0_vpp0_gdsc>,
> +                        <&video_cc_mvs0_vpp1_gdsc>,
> +                        <&video_cc_mvs0a_gdsc>;
> +        power-domain-names = "venus",
> +                             "vcodec0",
> +                             "mxc",
> +                             "mmcx",
> +                             "vpp0",
> +                             "vpp1",
> +                             "apv";
> +
> +        resets = <&gcc_video_axi0_clk_ares>,
> +                 <&gcc_video_axi1_clk_ares>,
> +                 <&video_cc_mvs0c_freerun_clk_ares>,
> +                 <&video_cc_mvs0_freerun_clk_ares>;
> +        reset-names = "bus0",
> +                      "bus1",
> +                      "core",
> +                      "vcodec0_core";
> +
> +        iris_opp_table: opp-table {
> +            compatible = "operating-points-v2";
> +
> +            opp-240000000 {
> +                opp-hz = /bits/ 64 <240000000 240000000 240000000 360000000>;
> +                required-opps = <&rpmhpd_opp_low_svs_d1>,
> +                                <&rpmhpd_opp_low_svs_d1>;

It's a DT and not the schema question, but please cross-check the OPP
points here. If I understand Taniya correctly, we should be using
corners from the PLL type rather than from the video_cc clock plan (they
differ for some reason). Downstream videocc driver also should have
correct rail corners for the PLLs.

> +            };
> +

-- 
With best wishes
Dmitry