Re: [PATCH v2 3/6] media: mali-c55: Fully reset the ISP configuration
From: Dan Scally
Date: Fri Mar 13 2026 - 12:07:22 EST
Hi Jacopo
On 13/03/2026 14:53, Jacopo Mondi wrote:
The Mali C55 driver uses an auto-suspend delay of 2000 milli-seconds.
As the delay is quite large, it is certainly possible that two
consecutive calls to enable_streams() do not go through a suspend of the
peripheral, meaning we cannot rely on POW register values for the ISP
configuration.
To prevent a streaming session to be initialized with settings from the
previous one, reset the full ISP configuration to know state disabling or
bypassing all the ISP blocks the driver supports.
Oh that's annoying - good spot...perhaps the auto-suspend delay should be reduced too, though I think this change is prudent anyway:
Reviewed-by: Daniel Scally <dan.scally@xxxxxxxxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Fixes: d5f281f3dd29 ("media: mali-c55: Add Mali-C55 ISP driver")
Signed-off-by: Jacopo Mondi <jacopo.mondi@xxxxxxxxxxxxxxxx>
---
.../media/platform/arm/mali-c55/mali-c55-params.c | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-params.c b/drivers/media/platform/arm/mali-c55/mali-c55-params.c
index c84a6047a570..773e5b6a2b7e 100644
--- a/drivers/media/platform/arm/mali-c55/mali-c55-params.c
+++ b/drivers/media/platform/arm/mali-c55/mali-c55-params.c
@@ -781,6 +781,43 @@ void mali_c55_params_init_isp_config(struct mali_c55 *mali_c55,
MALI_C55_REG_BYPASS_3_SQUARE_BE,
MALI_C55_REG_BYPASS_3_SQUARE_BE);
+ /* Bypass the sensor offset correction (BLS) module */
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BYPASS_3,
+ MALI_C55_REG_BYPASS_3_SENSOR_OFFSET_PRE_SH,
+ MALI_C55_REG_BYPASS_3_SENSOR_OFFSET_PRE_SH);
+
+ /* Configure 1x digital gain. */
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_DIGITAL_GAIN,
+ MALI_C55_DIGITAL_GAIN_MASK, 256);
+
+ /* Set all AWB gains to 1x. at both AWB configuration points*/
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_AWB_GAINS1,
+ MALI_C55_AWB_GAIN00_MASK, 256);
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_AWB_GAINS1,
+ MALI_C55_AWB_GAIN01_MASK,
+ MALI_C55_AWB_GAIN01(256));
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_AWB_GAINS2,
+ MALI_C55_AWB_GAIN10_MASK, 256);
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_AWB_GAINS2,
+ MALI_C55_AWB_GAIN11_MASK,
+ MALI_C55_AWB_GAIN11(256));
+
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_AWB_GAINS1_AEXP,
+ MALI_C55_AWB_GAIN00_MASK, 256);
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_AWB_GAINS1_AEXP,
+ MALI_C55_AWB_GAIN01_MASK,
+ MALI_C55_AWB_GAIN01(256));
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_AWB_GAINS2_AEXP,
+ MALI_C55_AWB_GAIN10_MASK, 256);
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_AWB_GAINS2_AEXP,
+ MALI_C55_AWB_GAIN11_MASK,
+ MALI_C55_AWB_GAIN11(256));
+
+ /* Bypass mesh shading corrections (LSC). */
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_MESH_SHADING_CONFIG,
+ MALI_C55_MESH_SHADING_ENABLE_MASK,
+ false);
+
/* Bypass the temper module */
mali_c55_ctx_write(mali_c55, MALI_C55_REG_BYPASS_2,
MALI_C55_REG_BYPASS_2_TEMPER);
@@ -802,6 +839,19 @@ void mali_c55_params_init_isp_config(struct mali_c55 *mali_c55,
/* Disable the colour correction matrix */
mali_c55_ctx_write(mali_c55, MALI_C55_REG_CCM_ENABLE, 0);
+
+ /* Disable AWB stats. */
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_METERING_CONFIG,
+ MALI_C55_AWB_DISABLE_MASK,
+ MALI_C55_AWB_DISABLE_MASK);
+
+ /* Disable auto-exposure 1024-bin histograms at both tap points. */
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_METERING_CONFIG,
+ MALI_C55_AEXP_HIST_DISABLE_MASK,
+ MALI_C55_AEXP_HIST_DISABLE);
+ mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_METERING_CONFIG,
+ MALI_C55_AEXP_IHIST_DISABLE_MASK,
+ MALI_C55_AEXP_IHIST_DISABLE);
}
void mali_c55_unregister_params(struct mali_c55 *mali_c55)