Re: [PATCH v2 1/1] x86/mce/amd: Fix VM crash during deferred error handling

[Borislav Petkov]

On Thu, Mar 12, 2026 at 11:44:04PM +0100, William Roche wrote:
> Yazen, could you also please tell us if an existing non-SMCA AMD hardware
> could crash on updating an SMCA register ?

So, the situation is this: if software needs to access a MCA_DESTATUS MSR
- which is part of AMD's MCA extensions - then software needs to check the
 smca bit.

So your patch is correct. The justification about it is not.

It should talk about how software should touch that MSR *only* *after* having
checked mce_flags.smca.

Because, it doesn't matter what KVM does or whoever - we all adhere to the hw
spec.

Because technically speaking, this code should blow up on non-SMCA machines
too because they do support deferred errors (Bulldozer for example) but they
will #GP on access to the MCA_DESTATUS MSRs as those are reserved there.

So please rewrite your commit message to state that. And then you can talk
about what the real-life situation is which caught this.

As to your use case - thanks for explaining it. If this is something which
people run, then it would be wonderful if we had a simple test script in the
kernel which verifies new changes don't break it and so that we can run it
periodically as part of testing.

HTH.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette