Re: [PATCH v6 4/4] iio: adc: ad4080: add support for AD4880 dual-channel ADC

[Jonathan Cameron]

On Fri, 13 Mar 2026 16:22:53 +0200
Andy Shevchenko <andriy.shevchenko@xxxxxxxxx> wrote:

> On Fri, Mar 13, 2026 at 01:58:53PM +0200, Antoniu Miclaus wrote:
> > Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC with
> > integrated fully differential amplifiers (FDA).
> > 
> > The AD4880 has two independent ADC channels, each with its own SPI
> > configuration interface. The driver uses spi_new_ancillary_device() to
> > create an additional SPI device for the second channel, allowing both
> > channels to share the same SPI bus with different chip selects.  
> 
> I am still not sure this is the best approach we can have.
> In any case, I have immediate questions here about regmap usage.

I think we have a fairly fundamental misalignment on what this is.

To my understanding (diagram on first page of the datasheet)
+ the functional block diagram on page 3 it's effectively two almost
entirely separate devices in one package (sharing of power etc) and
a few common wires for clocks references etc.  Pretty close to some
of the multi die devices we get for IMUs etc but with tighter coupling
that forces one driver (for the IMUs we just register separate drivers).

It 'might' use one SPI bus, or 2 or even 4 (if using separate data
interfaces).

Just to speed things up let me have a go at answering the questions.

> 
> - Why do we need to have a separate regmap per channel?

Propose an alternative? It's two independent interfaces, so you
could spin a special regmap to handle that, but it's much simpler
to just use standard stuff and keep them separate. Not to mention it
would either have to do external locking or falsely imply
there was any restriction on using both interfaces at once
(there isn't)

> - What is special about channel 0?

Nothing.

> - Is it okay to communicate with different channels simultaneously?

Yes. They are entirely parallel bits of silicon. Own state machines
and everything.
The configuration registers section of the datasheet says:
"Each channel has it's own independent configuration memory
accessible through it's separate configuration SPI interface."

>   Wouldn't be a nasty race with HW IO?

Nope. You are talking to different devices (more or less).

Jonathan