Re: [PATCH spi-next 04/11] spi: spi-fsl-lpspi: fsl_lpspi_set_watermark(): use FIELD_PREP() to encode FIFO Status register

[Mark Brown]

On Mon, Mar 16, 2026 at 05:49:48PM +0100, Marc Kleine-Budde wrote:
> On 16.03.2026 14:39:03, Mark Brown wrote:
> > On Mon, Mar 16, 2026 at 09:39:05AM +0100, Marc Kleine-Budde wrote:

> > The source of the watermark values appears to be

> > 	temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
> > 	fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
> > 	fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);

> > which suggests 4 bits of watermark not 3?  Or at least that something
> > isn't joined up somewhere.

> The param register's default value on the i.MX93 is:

> | LPSPI1–LPSPI3:  0002_0303h
> | LPSPI4:         0003_0303h
> | LPSPI5–LPSPI8:  0002_0303h

> This means a RX/TX-FIFO size of 1 << 3 == 8.

Right, so the parsing code is using the wrong mask to extract the width
here but with actual values it's fine.

> We can increase the the FCR_RXWATER and FCR_TXWATER to be 8 bits wide,
> the rest of the register is reserved.

It seems safer to restrict the mask used to extract the FIFO sizes, that
way we don't trample over any bits that get defined in future and people
comparing with the datasheet aren't confused.

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