Re: [PATCH v4 1/2] dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible

[Krzysztof Kozlowski]

On Mon, Mar 16, 2026 at 10:01:14AM -0500, nick.hawkins@xxxxxxx wrote:
> From: Nick Hawkins <nick.hawkins@xxxxxxx>
> 
> Add the 'hpe,gsc-dwcmshc' compatible string for the HPE GSC (ARM64
> Cortex-A53) BMC SoC eMMC controller.
> 
> The HPE GSC requires access to the MSHCCS register in the SoC system
> register block to configure SCG sync disable for HS200 RX delay-line
> phase selection.  The required 'hpe,gxp-sysreg' property takes a
> phandle to the existing 'hpe,gxp-sysreg' syscon and the MSHCCS
> register offset within that block.
> 
> The HPE GSC eMMC interface only exposes a single 'core' clock (no
> bus clock), so clocks/clock-names are constrained to a single item.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@xxxxxxx>
> ---
>  .../bindings/mmc/snps,dwcmshc-sdhci.yaml      | 32 +++++++++++++++++++
>  1 file changed, 32 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>

Best regards,
Krzysztof