Re: [PATCH v13 0/2] Add AMD MDB Endpoint and non-LL mode Support

[Vinod Koul]

On 11-03-26, 16:48, Devendra K Verma wrote:
> This series of patch support the following:
> 
>  - AMD MDB Endpoint Support, as part of this patch following are
>    added:
>    o AMD supported device ID and vendor ID (Xilinx)
>    o AMD MDB specific driver data
>    o AMD specific VSEC capabilities to retrieve the base of
>      phys address of MDB side DDR
>    o Logic to assign the offsets to LL and data blocks if
>      more number of channels are enabled than configured
>      in the given pci_data struct.
> 
>  - Addition of non-LL mode
>    o The IP supported non-LL mode functions
>    o Flexibility to choose non-LL mode via dma_slave_config
>      param peripheral_config, by the client for all the vendors
>      using HDMA IP.
>    o Allow IP utilization if LL mode is not available

There is trailing whitespace in patch2 and even then it fails for me on
dmaengine/next. Please rebase and resend

-- 
~Vinod