Re: [RFC PATCH v2] cxl/core: Work around CXL Port PM Init failure when ACS SV enabled

[Bjorn Helgaas]

On Wed, Mar 11, 2026 at 05:36:47PM +0100, Fabio M. De Francesco wrote:
> Compute Express Link (CXL) Specification Revision 4.0, Version 1.0, Section
> 8.1.5.1 - CXL Port Extension Status, Implementation Note, describes a
> scenario where a CXL downstream port may fail PM initialization:

> +++ b/include/uapi/linux/pci_regs.h
> @@ -1397,4 +1397,8 @@
>  #define   PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID		__GENMASK(15, 8)
>  #define   PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW	__GENMASK(31, 16)
>  
> +/* CXL 4.0 8.1.5.1: CXL Port Extension Status */
> +#define CXL_DVSEC_PORT_EXT_STATUS 0xA
> +#define CXL_DVSEC_PORT_EXT_STATUS_PM_INIT_COMP_MASK GENMASK(1, 0)

Please pay attention to the surrounding definitions.  This appears to
belong with the PCI_DVSEC_CXL_PORT above and should match the naming,
capitalization, and whitespace of those definitions.

My copy of CXL r4.0, sec 8.1.5.1, shows Port Power Management
Initialization Complete in the 16-bit CXL Port Extension Status at
offset 0Ah as a single bit, not the two bits from "GENMASK(1, 0)", so
I assume this should be "_BITUL(0)" instead.