[PATCH v2] arm64: dts: qcom: glymur: add coresight nodes
From: Jie Gan
Date: Wed Mar 18 2026 - 07:46:10 EST
Add CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF.
These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc and
some small subsystems, such as GCC, IPCC, PMU and so on.
Signed-off-by: Jie Gan <jie.gan@xxxxxxxxxxxxxxxx>
---
Changes in V2:
1. removed two cti devices due to GFX block is down
- cti@11c42000
- cti@11c4b000
2. changes two TPDM devices to static:
- tpdm-cdsp-cmsr
- tpdm-cdsp-cmsr2
Link to v1 - https://lore.kernel.org/all/20251230-add-coresight-nodes-for-glymur-v1-1-103b6d24f1ca@xxxxxxxxxxxxxxxx/
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 1097 ++++++++++++++++++++++++++++++++++
1 file changed, 1097 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index e269cec7942c..4d58d056c70d 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -341,6 +341,18 @@ domain_ss3: domain-sleep-0 {
};
};
+ dummy-sink {
+ compatible = "arm,coresight-dummy-sink";
+
+ in-ports {
+ port {
+ eud_in: endpoint {
+ remote-endpoint = <&swao_rep_out1>;
+ };
+ };
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-glymur", "qcom,scm";
@@ -4279,6 +4291,1035 @@ rx-pins {
};
};
+ stm: stm@10002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x0 0x10002000 0x0 0x1000>,
+ <0x0 0x16280000 0x0 0x180000>;
+ reg-names = "stm-base",
+ "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ tpda@10004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10004000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ qdss_tpda_in1: endpoint {
+ remote-endpoint = <&spdm_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ qdss_tpda_out: endpoint {
+ remote-endpoint = <&funnel0_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@1000f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1000f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ spdm_tpdm_out: endpoint {
+ remote-endpoint = <&qdss_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@10041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10041000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ funnel0_in0: endpoint {
+ remote-endpoint = <&tn_ag_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ funnel0_in6: endpoint {
+ remote-endpoint = <&qdss_tpda_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint = <&aoss_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@1102c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1102c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ gcc_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in36>;
+ };
+ };
+ };
+ };
+
+ tpdm@11180000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11180000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ cdsp_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@11185000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11185000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ cdsp_dpm1_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in5>;
+ };
+ };
+ };
+ };
+
+ tpdm@11186000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11186000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ cdsp_dpm2_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in6>;
+ };
+ };
+ };
+ };
+
+ tpda@11188000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x11188000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ cdsp_tpda_in0: endpoint {
+ remote-endpoint = <&cdsp_tpdm_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ cdsp_tpda_in1: endpoint {
+ remote-endpoint = <&cdsp_llm_tpdm_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ cdsp_tpda_in2: endpoint {
+ remote-endpoint = <&cdsp_llm2_tpdm_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ cdsp_tpda_in3: endpoint {
+ remote-endpoint = <&cdsp_cmsr_tpdm_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ cdsp_tpda_in4: endpoint {
+ remote-endpoint = <&cdsp_cmsr2_tpdm_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ cdsp_tpda_in5: endpoint {
+ remote-endpoint = <&cdsp_dpm1_tpdm_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ cdsp_tpda_in6: endpoint {
+ remote-endpoint = <&cdsp_dpm2_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ cdsp_tpda_out: endpoint {
+ remote-endpoint = <&cdsp_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@11189000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x11189000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ cdsp_funnel_in0: endpoint {
+ remote-endpoint = <&cdsp_tpda_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ cdsp_funnel_out: endpoint {
+ remote-endpoint = <&tn_ag_in53>;
+ };
+ };
+ };
+ };
+
+ cti@11193000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x11193000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ cti@111ab000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x111ab000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ tpdm@111d0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ qm_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in35>;
+ };
+ };
+ };
+ };
+
+ tn@11200000 {
+ compatible = "qcom,coresight-tnoc", "arm,primecell";
+ reg = <0x0 0x11200000 0x0 0x4200>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+
+ tn_ag_in6: endpoint {
+ remote-endpoint = <&mm_dsb_tpdm_out>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ tn_ag_in16: endpoint {
+ remote-endpoint = <&east_dsb_tpdm_out>;
+ };
+ };
+
+ port@21 {
+ reg = <0x21>;
+
+ tn_ag_in33: endpoint {
+ remote-endpoint = <&west_dsb_tpdm_out>;
+ };
+ };
+
+ port@23 {
+ reg = <0x23>;
+
+ tn_ag_in35: endpoint {
+ remote-endpoint = <&qm_tpdm_out>;
+ };
+ };
+
+ port@24 {
+ reg = <0x24>;
+
+ tn_ag_in36: endpoint {
+ remote-endpoint = <&gcc_tpdm_out>;
+ };
+ };
+
+ port@32 {
+ reg = <0x32>;
+
+ tn_ag_in50: endpoint {
+ remote-endpoint = <&pcie_rscc_tpda_out>;
+ };
+ };
+
+ port@35 {
+ reg = <0x35>;
+
+ tn_ag_in53: endpoint {
+ remote-endpoint = <&cdsp_funnel_out>;
+ };
+ };
+
+ port@3f {
+ reg = <0x3f>;
+
+ tn_ag_in63: endpoint {
+ remote-endpoint = <¢er_dsb_tpdm_out>;
+ };
+ };
+
+ port@40 {
+ reg = <0x40>;
+
+ tn_ag_in64: endpoint {
+ remote-endpoint = <&ipcc_cmb_tpdm_out>;
+ };
+ };
+
+ port@41 {
+ reg = <0x41>;
+
+ tn_ag_in65: endpoint {
+ remote-endpoint = <&qrng_tpdm_out>;
+ };
+ };
+
+ port@42 {
+ reg = <0x42>;
+
+ tn_ag_in66: endpoint {
+ remote-endpoint = <&pmu_tpdm_out>;
+ };
+ };
+
+ port@43 {
+ reg = <0x43>;
+
+ tn_ag_in67: endpoint {
+ remote-endpoint = <&rdpm_west_cmb0_tpdm_out>;
+ };
+ };
+
+ port@44 {
+ reg = <0x44>;
+
+ tn_ag_in68: endpoint {
+ remote-endpoint = <&rdpm_west_cmb1_tpdm_out>;
+ };
+ };
+
+ port@45 {
+ reg = <0x45>;
+
+ tn_ag_in69: endpoint {
+ remote-endpoint = <&rdpm_west_cmb2_tpdm_out>;
+ };
+ };
+
+ port@4b {
+ reg = <0x4b>;
+
+ tn_ag_in75: endpoint {
+ remote-endpoint = <&south_dsb2_tpdm_out>;
+ };
+ };
+
+ port@52 {
+ reg = <0x52>;
+
+ tn_ag_in82: endpoint {
+ remote-endpoint = <&south_dsb_tpdm_out>;
+ };
+ };
+
+ port@53 {
+ reg = <0x53>;
+
+ tn_ag_in83: endpoint {
+ remote-endpoint = <¢er_dsb1_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tn_ag_out: endpoint {
+ remote-endpoint = <&funnel0_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@11207000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11207000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ mm_dsb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@1120b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1120b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ east_dsb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in16>;
+ };
+ };
+ };
+ };
+
+ tpdm@11213000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11213000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ west_dsb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in33>;
+ };
+ };
+ };
+ };
+
+ tpdm@11219000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11219000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ center_dsb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in63>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ ipcc_cmb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in64>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ qrng_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in65>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ pmu_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in66>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ rdpm_west_cmb0_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in67>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121e000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ rdpm_west_cmb1_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in68>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ rdpm_west_cmb2_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in69>;
+ };
+ };
+ };
+ };
+
+ tpdm@11220000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11220000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ center_dsb1_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in83>;
+ };
+ };
+ };
+ };
+
+ tpdm@11224000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11224000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ south_dsb2_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in75>;
+ };
+ };
+ };
+ };
+
+ tpdm@11228000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11228000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ south_dsb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in82>;
+ };
+ };
+ };
+ };
+
+ tpdm@11470000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11470000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ pcie_rscc_tpdm_out: endpoint {
+ remote-endpoint = <&pcie_rscc_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@11471000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x11471000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ pcie_rscc_tpda_in0: endpoint {
+ remote-endpoint = <&pcie_rscc_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ pcie_rscc_tpda_out: endpoint {
+ remote-endpoint = <&tn_ag_in50>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c03000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c03000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio4_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in4>;
+ };
+ };
+ };
+ };
+
+ funnel@11c04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x11c04000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@5 {
+ reg = <5>;
+
+ aoss_funnel_in5: endpoint {
+ remote-endpoint = <&aoss_tpda_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ aoss_funnel_in6: endpoint {
+ remote-endpoint = <&funnel0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ aoss_funnel_out: endpoint {
+ remote-endpoint = <&etf0_in>;
+ };
+ };
+ };
+ };
+
+ tmc_etf: tmc@11c05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x11c05000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etf0_in: endpoint {
+ remote-endpoint = <&aoss_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf0_out: endpoint {
+ remote-endpoint = <&swao_rep_in>;
+ };
+ };
+ };
+ };
+
+ replicator@11c06000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x11c06000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ swao_rep_in: endpoint {
+ remote-endpoint = <&etf0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ swao_rep_out1: endpoint {
+ remote-endpoint = <&eud_in>;
+ };
+ };
+ };
+ };
+
+ tpda@11c08000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x11c08000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ aoss_tpda_in0: endpoint {
+ remote-endpoint = <&swao_prio0_tpdm_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ aoss_tpda_in1: endpoint {
+ remote-endpoint = <&swao_prio1_tpdm_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ aoss_tpda_in2: endpoint {
+ remote-endpoint = <&swao_prio2_tpdm_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ aoss_tpda_in3: endpoint {
+ remote-endpoint = <&swao_prio3_tpdm_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ aoss_tpda_in4: endpoint {
+ remote-endpoint = <&swao_prio4_tpdm_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ aoss_tpda_in5: endpoint {
+ remote-endpoint = <&swao_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ aoss_tpda_out: endpoint {
+ remote-endpoint = <&aoss_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c09000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio0_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c0a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c0a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio1_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c0b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c0b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio2_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c0c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c0c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio3_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c0d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c0d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in5>;
+ };
+ };
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,glymur-smmu-500",
"qcom,smmu-500",
@@ -5910,4 +6951,60 @@ gpuss-1-critical {
};
};
};
+
+ tpdm-cdsp-llm {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ cdsp_llm_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm-cdsp-llm2 {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ cdsp_llm2_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm-cdsp-cmsr {
+ compatible = "qcom,coresight-static-tpdm";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,dsb-element-bits = <32>;
+
+ out-ports {
+ port {
+ cdsp_cmsr_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm-cdsp-cmsr2 {
+ compatible = "qcom,coresight-static-tpdm";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,dsb-element-bits = <32>;
+
+ out-ports {
+ port {
+ cdsp_cmsr2_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in4>;
+ };
+ };
+ };
+ };
};
---
base-commit: b84a0ebe421ca56995ff78b66307667b62b3a900
change-id: 20260315-add-coresight-dt-nodes-for-glymur-ff935bf84e19
Best regards,
--
Jie Gan <jie.gan@xxxxxxxxxxxxxxxx>