Re: [PATCH v2 5/6] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support

[Kathiravan Thirumoorthy]

On 3/18/2026 5:14 PM, Konrad Dybcio wrote:
> On 3/18/26 9:39 AM, Kathiravan Thirumoorthy wrote:
> > Add initial device tree support for the Qualcomm IPQ5210 SoC and
> > rdp504 board.
> >
> > Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@xxxxxxxxxxxxxxxx>
> > ---
> [...]
>
> > +&sdhc {
> > +	max-frequency = <192000000>;
> > +	bus-width = <4>;
> > +	mmc-ddr-1_8v;
> > +	mmc-hs200-1_8v;
> > +	pinctrl-0 = <&sdhc_default_state>;
> > +	pinctrl-names = "default";
> > +	status = "okay";
> nit: Please keep a uniform \n before 'status', file-wide

Ack. I missed this to take care in RDP DTS.

> [...]
>
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53";
> > +			reg = <0x0>;
> > +			enable-method = "psci";
> > +			next-level-cache = <&l2_0>;
> Since we have PSCI, is there some sort of cpuidle?

Yeah, there is a plan to support but it is under development. Once it is 
available and validate, I will submit the incremental patches.

> [...]
>
> > +		intc: interrupt-controller@b000000 {
> > +			compatible = "qcom,msm-qgic2";
> > +			interrupt-controller;
> > +			#interrupt-cells = <3>;
> > +			reg = <0x0 0xb000000 0x0 0x1000>,  /* GICD */
> > +			      <0x0 0xb002000 0x0 0x1000>,  /* GICC */
> > +			      <0x0 0xb001000 0x0 0x1000>,  /* GICH */
> > +			      <0x0 0xb004000 0x0 0x1000>;  /* GICV */
> let's drop these comments

Ack.

> [...]
>
> > +		timer@b120000 {
> > +			compatible = "arm,armv7-timer-mem";
> > +			reg = <0x0 0xb120000 0x0 0x1000>;
> Please pad the address part of reg with leading zeroes to 8 hex digits
> (i.e. 0x0b120000 etc.)

Ack. Will take care of this next spin

> otherwise I think lgtm

Thanks!

> Konrad