[PATCH 0/2] A proposal to add a virtual clock controller guard.

[Vyacheslav Yurkov via B4 Relay]

The clock controller guard driver acts as clock provider and provides only
one clock that consumers can check to make sure whether all other conditions
are met in order to enable other peripehrals. This can be seen as 1-to-N
clock relation, thus consumers care only about one clock and not about N.

The usage example for such a driver is when peripherals depend on PLLs in
a FPGA, which can't be directly accessed by the CPU, but need a GPIO pin
to chekc whether clock is actually usable.

Signed-off-by: Vyacheslav Yurkov <uvv.mail@xxxxxxxxx>
Signed-off-by: Vyacheslav Yurkov <V.Yurkov.EXT@xxxxxxxxxx>
---
Vyacheslav Yurkov (2):
      clk: Add clock controller guard
      dt-bindings: Add clock guard DT description

 .../bindings/clock/clock-controller-guard.yaml     |  79 +++++
 drivers/clk/Kconfig                                |  12 +
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clkctrl-guard.c                        | 334 +++++++++++++++++++++
 4 files changed, 426 insertions(+)
---
base-commit: 4f3df2e5ea69f5717d2721922aff263c31957548
change-id: 20260318-feature-clock-guard-f20a2c35b965

Best regards,
-- 
Vyacheslav Yurkov <V.Yurkov.EXT@xxxxxxxxxx>