RE: [PATCH v5 6/9] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 18 March 2026 15:12
> Subject: Re: [PATCH v5 6/9] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
> 
> Hi Biju,
> 
> On Wed, 18 Mar 2026 at 09:42, Biju <biju.das.au@xxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Add the initial DTSI for the RZ/G3L SoC.
> > The files in this commit have the following meaning:
> >   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
> >   - r9a08g046l48.dtsi: RZ/G3L R9A08G046L48 SoC-specific parts
> >
> > Add placeholders to reuse the code for the Renesas SMARC II carrier
> > board.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > v4->v5:
> >  * No change
> > v3->v4:
> >  * Fixed typo R0A08G046L->R9A08G046L in commit description
> >  * Dropped R9A08G046L46 from commit description
> >  * Dropped unused audio_clk{1,2} andcan_clk device nodes
> >  * Reordered i2c device node and updated reg entries by using lower-case
> >    hexadecimal number
> >  * Added placeholder in pinctrl node
> >  * Dropped unused DMAC device node
> >  * Added pcie node with placeholder
> 
> Thanks for the update!
> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > @@ -0,0 +1,215 @@
> 
> > +       soc: soc {
> > +               compatible = "simple-bus";
> > +               #address-cells = <2>;
> > +               #size-cells = <2>;
> > +               ranges;
> 
> > +               pcie: pcie@11e40000 {
> > +                       reg = <0 0x11e40000 0 0x10000>;
> > +                       ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
> > +                       /* Map all possible DRAM ranges (4 GB). */
> > +                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
> > +                       bus-range = <0x0 0xff>;
> > +                       device_type = "pci";
> > +                       #address-cells = <3>;
> > +                       #size-cells = <2>;
> > +                       /* placeholder */
> > +
> > +                       pcie_port0: pcie@0,0 {
> > +                               reg = <0x0 0x0 0x0 0x0 0x0>;
> > +                               ranges;
> > +                               device_type = "pci";
> > +                               #address-cells = <3>;
> > +                               #size-cells = <2>;
> > +                               /* placeholder */
> > +                       };
> > +               };
> 
> That's a rather large placeholder. Do you need all of that now?

We can drop the below ones. I will fix this in next version

> > +                       /* Map all possible DRAM ranges (4 GB). */
> > +                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
> > +                       bus-range = <0x0 0xff>;

Cheers,
Biju