RE: [PATCH 08/20] vfio/pci: Add vfio-cxl Kconfig and build infrastructure

[Manish Honap]

> -----Original Message-----
> From: Jonathan Cameron <jonathan.cameron@xxxxxxxxxx>
> Sent: 13 March 2026 17:57
> To: Manish Honap <mhonap@xxxxxxxxxx>
> Cc: Aniket Agashe <aniketa@xxxxxxxxxx>; Ankit Agrawal <ankita@xxxxxxxxxx>;
> Alex Williamson <alwilliamson@xxxxxxxxxx>; Vikram Sethi
> <vsethi@xxxxxxxxxx>; Jason Gunthorpe <jgg@xxxxxxxxxx>; Matt Ochs
> <mochs@xxxxxxxxxx>; Shameer Kolothum Thodi <skolothumtho@xxxxxxxxxx>;
> alejandro.lucero-palau@xxxxxxx; dave@xxxxxxxxxxxx; dave.jiang@xxxxxxxxx;
> alison.schofield@xxxxxxxxx; vishal.l.verma@xxxxxxxxx; ira.weiny@xxxxxxxxx;
> dan.j.williams@xxxxxxxxx; jgg@xxxxxxxx; Yishai Hadas <yishaih@xxxxxxxxxx>;
> kevin.tian@xxxxxxxxx; Neo Jia <cjia@xxxxxxxxxx>; Tarun Gupta (SW-GPU)
> <targupta@xxxxxxxxxx>; Zhi Wang <zhiw@xxxxxxxxxx>; Krishnakant Jaju
> <kjaju@xxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx; linux-
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> Subject: Re: [PATCH 08/20] vfio/pci: Add vfio-cxl Kconfig and build
> infrastructure
> 
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> 
> On Thu, 12 Mar 2026 02:04:28 +0530
> mhonap@xxxxxxxxxx wrote:
> 
> > From: Manish Honap <mhonap@xxxxxxxxxx>
> >
> > Introduce the Kconfig option CONFIG_VFIO_CXL_CORE and the necessary
> > build rules to compile CXL Type-2 passthrough support into the
> > vfio-pci-core module.  The new option depends on VFIO_PCI_CORE,
> > CXL_BUS and CXL_MEM.
> >
> > Wire up the detection and cleanup entry-point stubs in
> > vfio_pci_core_register_device() and vfio_pci_core_unregister_device()
> > so that subsequent patches can fill in the CXL-specific logic without
> > touching the vfio-pci-core flow again.
> >
> > The vfio_cxl_core.c file added here is an empty skeleton; the actual
> > CXL detection and initialisation code is introduced in the following
> > patch to keep this build-system patch reviewable on its own.
> >
> > Signed-off-by: Manish Honap <mhonap@xxxxxxxxxx>
> Hi Manish,
> A few trivial things inline.
> 
> > diff --git a/drivers/vfio/pci/cxl/vfio_cxl_core.c
> > b/drivers/vfio/pci/cxl/vfio_cxl_core.c
> > new file mode 100644
> > index 000000000000..7698d94e16be
> > --- /dev/null
> > +++ b/drivers/vfio/pci/cxl/vfio_cxl_core.c
> > @@ -0,0 +1,35 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * VFIO CXL Core - Common infrastructure for CXL Type-2 device
> > +variant drivers
> > + *
> > + * Copyright (c) 2026, NVIDIA CORPORATION & AFFILIATES. All rights
> > +reserved
> > + *
> > + * This module provides common functionality for VFIO variant drivers
> > +that
> > + * support CXL Type-2 devices (cache-coherent accelerators with
> attached memory).
> As I mentioned for docs, that definition needs some finessing as also CXL
> Type3 devices, though intention is not the ones compliant with the class
> code as those can be nicely paravirtualized.
> 
> There is a whole class of CXL.mem only devices with various forms of
> accelerator that never need CXL.cache and so aren't Type 2.
> 
> E.g. Compressed memory type 3 devices are known to be in the wild.

Okay, I have updated this wording to specify the CXL capable device expectation.

> 
> > + */
> > +
> > +#include <linux/vfio_pci_core.h>
> > +#include <linux/pci.h>
> > +#include <cxl/cxl.h>
> > +#include <cxl/pci.h>
> > +
> > +#include "../vfio_pci_priv.h"
> > +#include "vfio_cxl_priv.h"
> > +
> > +MODULE_IMPORT_NS("CXL");
> 
> Most often I've seen this added at the end of file next other MODULE_X
> calls.
> Whilse we don't have any of those here, still feels like a sensible place
> to put it.
> 

Moved this to EOF.

> 
> > +
> > +/**
> > + * vfio_pci_cxl_detect_and_init - Detect and initialize CXL Type-2
> > +device
> > + * @vdev: VFIO PCI device
> > + *
> > + * Called from vfio_pci_core_register_device(). Detects CXL DVSEC
> > +capability
> > + * and initializes CXL features. On failure vdev->cxl remains NULL
> > +and the
> > + * device operates as a standard PCI device.
> > + */
> > +void vfio_pci_cxl_detect_and_init(struct vfio_pci_core_device *vdev)
> > +{ }
> > +
> > +void vfio_pci_cxl_cleanup(struct vfio_pci_core_device *vdev) { }