Re: [PATCH v5 5/8] clk: amlogic: Add A5 clock peripherals controller driver

[Chuan Liu]

Hi Jerome,


> > > > +#define A5_COMP_SEL(_name, _reg, _shift, _mask, _pdata, _table) \
> > > > +     MESON_COMP_SEL(a5_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0)
> > > > +
> > > > +#define A5_COMP_DIV(_name, _reg, _shift, _width) \
> > > > +     MESON_COMP_DIV(a5_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
> > > > +
> > > > +#define A5_COMP_GATE(_name, _reg, _bit, _iflags) \
> > > > +     MESON_COMP_GATE(a5_, _name, _reg, _bit, CLK_SET_RATE_PARENT | (_iflags))
> > > > +
> > > At the top. like C3 and T7
> >
> > Except for A5_COMP_SEL, which differs slightly from T7 due to the
> > additional "_table" parameter, the other macros are consistent with T7.
> >
> > I also asked for your feedback on this in V4 and received your
> > confirmation. Is there anything here that still needs to be updated?
>
> Reviewing these long patches takes time. I tend to stop reviewing when I
> noticed some feedback was ignored, especially when it is recurrent
> problem. I've told you that already. It is up to you to make sure you are
> not missing anything before re-submitting if you don't want to waste time.

It has been nearly two months since I sent out the V6 version [1], and I 
haven't received your feedback. I'm not sure whether this is because you 
still have concerns about this part of the change?

This approach was already confirmed by you in V4 [2], and I also 
explained it there. There has been no change to this part in V6 compared 
to V5.

This email is not intended to rush you, but just to confirm. If there 
are no objections, please feel free to ignore this message. If you do 
have any concerns, please let me know.

[1] 
https://lore.kernel.org/all/20260123-a5-clk-v6-0-6d3bbf0ec1ea@xxxxxxxxxxx/
[2] 
https://lore.kernel.org/all/1jldice808.fsf@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx/

> > [...]
>
> --
> Jerome