Re: [PATCH v13 3/5] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux

[Linus Walleij]

On Wed, Mar 18, 2026 at 12:04 PM Conor Dooley <conor@xxxxxxxxxx> wrote:

> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> On PolarFire SoC there are more GPIO interrupts than there are interrupt
> lines available on the PLIC, and a runtime configurable mux is used to
> decide which interrupts are assigned direct connections to the PLIC &
> which are relegated to sharing a line.
>
> Reviewed-by: Herve Codina <herve.codina@xxxxxxxxxxx>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>

Rob explained to me how this works so looks good to me!
Reviewed-by: Linus Walleij <linusw@xxxxxxxxxx>

Yours,
Linus Walleij