Re: [PATCH v10 2/7] PCI: dwc: Record integrated eDMA register window

[Koichiro Den]

On Sat, Mar 21, 2026 at 07:51:08PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Mar 02, 2026 at 04:14:22PM +0900, Koichiro Den wrote:
> > Some DesignWare PCIe controllers integrate an eDMA block whose registers
> > are located in a dedicated register window. Endpoint function drivers
> > may need the physical base and size of this window to map/expose it to a
> > peer.
> > 
> 
> This sounds exactly like 'Remote eDMA' concept where the eDMA registers are
> exposed over BAR and programmed by the host. So why this duplication and why
> can't you reuse remote eDMA?

Thanks for reviewing.

The intent is not to introduce another "remote eDMA" scheme. I am trying to
reuse the same model, but what is missing today is the EP-side resource
plumbing.

In-tree today, the remote path is effectively host-driven, i.e. a driver such as
dw-edma-pcie discovers and maps the remote eDMA windows after enumeration. For a
DesignWare EP, we still need a way for the EPC/EPF side to describe what
integrated eDMA resources are available to be exposed to the RC.

This patch is only the preparatory part. Today, pci->edma.reg_base is just a
local kernel VA, but the EP side needs the physical base/size so it can expose
that window in a BAR, or reuse a reserved BAR window as-is (e.g. RK3588).
Patch 3 then exports the eDMA register / LL / doorbell resources via
get_aux_resources().

So this is meant to make existing remote-eDMA style exposure usable from the PCI
endpoint framework, not to duplicate it. I can revise the commit message to
better explain this.

Best regards,
Koichiro

> 
> - Mani
> 
> > Record the physical base and size of the integrated eDMA register window
> > in struct dw_pcie.
> > 
> > Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> > Tested-by: Niklas Cassel <cassel@xxxxxxxxxx>
> > Signed-off-by: Koichiro Den <den@xxxxxxxxxxxxx>
> > ---
> >  drivers/pci/controller/dwc/pcie-designware.c | 4 ++++
> >  drivers/pci/controller/dwc/pcie-designware.h | 2 ++
> >  2 files changed, 6 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 5741c09dde7f..f82ed189f6ae 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -162,8 +162,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
> >  			pci->edma.reg_base = devm_ioremap_resource(pci->dev, res);
> >  			if (IS_ERR(pci->edma.reg_base))
> >  				return PTR_ERR(pci->edma.reg_base);
> > +			pci->edma_reg_phys = res->start;
> > +			pci->edma_reg_size = resource_size(res);
> >  		} else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {
> >  			pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;
> > +			pci->edma_reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET;
> > +			pci->edma_reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET;
> >  		}
> >  	}
> >  
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index ae6389dd9caa..52f26663e8b1 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -541,6 +541,8 @@ struct dw_pcie {
> >  	int			max_link_speed;
> >  	u8			n_fts[2];
> >  	struct dw_edma_chip	edma;
> > +	phys_addr_t		edma_reg_phys;
> > +	resource_size_t		edma_reg_size;
> >  	bool			l1ss_support;	/* L1 PM Substates support */
> >  	struct clk_bulk_data	app_clks[DW_PCIE_NUM_APP_CLKS];
> >  	struct clk_bulk_data	core_clks[DW_PCIE_NUM_CORE_CLKS];
> > -- 
> > 2.51.0
> > 
> 
> -- 
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