Re: [PATCH v4 03/11] arm64: dts: qcom: kaanapali: Add power-domain and iface clk for ice node

[Kuldeep Singh]

On 3/23/2026 2:47 PM, Harshal Dev wrote:
> Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
> for its own resources. Before accessing ICE hardware during probe, to
> avoid potential unclocked register access issues (when clk_ignore_unused
> is not passed on the kernel command line), in addition to the 'core' clock
> the 'iface' clock should also be turned on by the driver. This can only be
> done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the
> GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for
> kaanapali.
> 
> Fixes: 2eeb5767d53f4 ("arm64: dts: qcom: Introduce Kaanapali SoC")
> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
> Signed-off-by: Harshal Dev <harshal.dev@xxxxxxxxxxxxxxxx>

Reviewed-by: Kuldeep Singh <kuldeep.singh@xxxxxxxxxxxxxxxx>

> ---
>  arch/arm64/boot/dts/qcom/kaanapali.dtsi | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> index 9ef57ad0ca71..52af56e09168 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> @@ -868,7 +868,11 @@ ice: crypto@1d88000 {
>  				     "qcom,inline-crypto-engine";
>  			reg = <0x0 0x01d88000 0x0 0x18000>;
>  
> -			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> +			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
> +				 <&gcc GCC_UFS_PHY_AHB_CLK>;
> +			clock-names = "core",
> +				      "iface";
> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>  		};
>  
>  		tcsr_mutex: hwlock@1f40000 {
> 

-- 
Regards
Kuldeep