Re: [PATCH v4 2/2] arm64: dts: cix: Add scmi powerdomain nodes for sky1

[Peter Chen]

On 26-03-13 19:49:14, Gary Yang wrote:
> Add a second SCMI channel using SMC transport to communicate with TF-A
> for power domain management on the Sky1 SoC.
> 
> Signed-off-by: Gary Yang <gary.yang@xxxxxxxxxxx>

Applied, thanks.

Peter
> ---
>  arch/arm64/boot/dts/cix/sky1-power.h | 33 ++++++++++++++++++++++++++++
>  arch/arm64/boot/dts/cix/sky1.dtsi    | 21 ++++++++++++++++++
>  2 files changed, 54 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/cix/sky1-power.h
> 
> diff --git a/arch/arm64/boot/dts/cix/sky1-power.h b/arch/arm64/boot/dts/cix/sky1-power.h
> new file mode 100644
> index 000000000000..53f4a3af36b3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/cix/sky1-power.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright 2026 Cix Technology Group Co., Ltd.
> + */
> +
> +#ifndef __SKY1_POWER_H__
> +#define __SKY1_POWER_H__
> +
> +/* The Rich OS need flow the macro */
> +#define SKY1_PD_AUDIO		0
> +#define SKY1_PD_PCIE_CTRL0	1
> +#define SKY1_PD_PCIE_DUMMY	2
> +#define SKY1_PD_PCIEHUB		3
> +#define SKY1_PD_MMHUB		4
> +#define SKY1_PD_MMHUB_SMMU	5
> +#define SKY1_PD_DPU0		6
> +#define SKY1_PD_DPU1		7
> +#define SKY1_PD_DPU2		8
> +#define SKY1_PD_DPU3		9
> +#define SKY1_PD_DPU4		10
> +#define SKY1_PD_VPU_TOP		11
> +#define SKY1_PD_VPU_CORE0	12
> +#define SKY1_PD_VPU_CORE1	13
> +#define SKY1_PD_VPU_CORE2	14
> +#define SKY1_PD_VPU_CORE3	15
> +#define SKY1_PD_NPU_CORE0	16
> +#define SKY1_PD_NPU_CORE1	17
> +#define SKY1_PD_NPU_CORE2	18
> +#define SKY1_PD_NPU_TOP		19
> +#define SKY1_PD_ISP0		20
> +#define SKY1_PD_GPU		21
> +
> +#endif
> diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
> index 64b76905cbff..495ea91a63f5 100644
> --- a/arch/arm64/boot/dts/cix/sky1.dtsi
> +++ b/arch/arm64/boot/dts/cix/sky1.dtsi
> @@ -6,6 +6,7 @@
>  
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/clock/cix,sky1.h>
> +#include "sky1-power.h"
>  
>  / {
>  	interrupt-parent = <&gic>;
> @@ -168,6 +169,19 @@ scmi_clk: protocol@14 {
>  				#clock-cells = <1>;
>  			};
>  		};
> +
> +		ap_to_tfa_scmi: scmi-1 {
> +			compatible = "arm,scmi-smc";
> +			arm,smc-id = <0xc2000001>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			shmem = <&ap_tfa_scmi_mem>;
> +
> +			smc_devpd: protocol@11 {
> +				reg = <0x11>;
> +				#power-domain-cells = <1>;
> +			};
> +		};
>  	};
>  
>  	pmu-a520 {
> @@ -428,6 +442,7 @@ pcie_x8_rc: pcie@a010000 {
>  			#size-cells = <2>;
>  			bus-range = <0xc0 0xff>;
>  			device_type = "pci";
> +			power-domains = <&smc_devpd SKY1_PD_PCIE_CTRL0>;
>  			#interrupt-cells = <1>;
>  			interrupt-map-mask = <0 0 0 0x7>;
>  			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
> @@ -572,6 +587,12 @@ iomuxc_s5: pinctrl@16007000 {
>  			compatible = "cix,sky1-pinctrl-s5";
>  			reg = <0x0 0x16007000 0x0 0x1000>;
>  		};
> +
> +		ap_tfa_scmi_mem: shmem@84380000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x0 0x84380000 0x0 0x80>;
> +			reg-io-width = <4>;
> +		};
>  	};
>  
>  	timer {
> -- 
> 2.49.0
> 

-- 

Best regards,
Peter