[PATCH v8 07/14] PCI: tegra194: Disable direct speed change for Endpoint

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@xxxxxxxxxx>

Pre-silicon simulation showed the Endpoint initiating speed change after
secondary bus reset; the HW team recommended disabling this feature in the
Endpoint. Disable direct speed change for the Endpoint so it does not
initiate speed change after physical layer link up at gen1, leaving speed
change ownership with the host.

Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Reviewed-by: Jon Hunter <jonathanh@xxxxxxxxxx>
Tested-by: Jon Hunter <jonathanh@xxxxxxxxxx>
Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@xxxxxxxxxx>
---
Changes V8: Fix commit mesaage
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index e0b17ad3052d..0be701e58238 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1805,6 +1805,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 
 	reset_control_deassert(pcie->core_rst);
 
+	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+	val &= ~PORT_LOGIC_SPEED_CHANGE;
+	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+
 	if (pcie->update_fc_fixup) {
 		val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
 		val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
-- 
2.34.1