Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Dmitry Baryshkov]

On Tue, Mar 24, 2026 at 05:28:48PM +0530, Nitin Rawat wrote:
> 
> 
> On 3/24/2026 2:44 PM, Konrad Dybcio wrote:
> > On 3/23/26 8:25 PM, Dmitry Baryshkov wrote:
> > > On Mon, Mar 23, 2026 at 08:57:12PM +0200, Abel Vesa wrote:
> > > > According to internal documentation, the UFS AXI PHY clock requires
> > > > FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
> > > > the UFS controller fails when operating in MCQ mode, which is already
> > > > enabled in the device tree.
> > > > 
> > > > The UFS PHY ICE core clock already has this bit set, so apply the same
> > > > configuration to the UFS PHY AXI clock.
> > > > 
> > > > Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
> > > > Reported-by: Nitin Rawat <nitin.rawat@xxxxxxxxxxxxxxxx>
> > > > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>
> > > > ---
> > > >   drivers/clk/qcom/gcc-eliza.c | 3 ++-
> > > >   1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
> > > 
> > > Do we need to apply the same fix to any other platform?
> > 
> > Most of them, actually
> Only SM8850 is missing.

Could you please fix it too (in a new iteration or as a followup).

> SM8650 and SM8750 has the change.
> 
> Regards,
> NItin
> 
> 
> > 
> > Konrad
> 

-- 
With best wishes
Dmitry