Re: [PATCH 2/2] clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}

[Lad, Prabhakar]

On Tue, Mar 24, 2026 at 10:58 PM Fabrizio Castro
<fabrizio.castro.jz@xxxxxxxxxxx> wrote:
>
> The Renesas RZ/V2N SoC (a.k.a. r9a09g056) comes with 4 watchdogs.
>
> As it turns out, it only makes sense for Linux to have access to
> WDT1.
>
> Remove the clock and reset entries for WDT{0,2,3} to prevent
> interfering with the CM33 core.
>
> This change is harmless as only WDT1 is currently used in Linux,
> there are no users for the WDT{0,2,3} IPs.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> ---
>  drivers/clk/renesas/r9a09g056-cpg.c | 15 ---------------
>  1 file changed, 15 deletions(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Cheers,
Prabhakar

> diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
> index 549c882f9a18..2ff2935aeb0d 100644
> --- a/drivers/clk/renesas/r9a09g056-cpg.c
> +++ b/drivers/clk/renesas/r9a09g056-cpg.c
> @@ -273,22 +273,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
>                                                 BUS_MSTOP(11, BIT(15))),
>         DEF_MOD("gtm_7_pclk",                   CLK_PLLCLN_DIV16, 4, 10, 2, 10,
>                                                 BUS_MSTOP(12, BIT(0))),
> -       DEF_MOD("wdt_0_clkp",                   CLK_PLLCM33_DIV16, 4, 11, 2, 11,
> -                                               BUS_MSTOP(3, BIT(10))),
> -       DEF_MOD("wdt_0_clk_loco",               CLK_QEXTAL, 4, 12, 2, 12,
> -                                               BUS_MSTOP(3, BIT(10))),
>         DEF_MOD("wdt_1_clkp",                   CLK_PLLCLN_DIV16, 4, 13, 2, 13,
>                                                 BUS_MSTOP(1, BIT(0))),
>         DEF_MOD("wdt_1_clk_loco",               CLK_QEXTAL, 4, 14, 2, 14,
>                                                 BUS_MSTOP(1, BIT(0))),
> -       DEF_MOD("wdt_2_clkp",                   CLK_PLLCLN_DIV16, 4, 15, 2, 15,
> -                                               BUS_MSTOP(5, BIT(12))),
> -       DEF_MOD("wdt_2_clk_loco",               CLK_QEXTAL, 5, 0, 2, 16,
> -                                               BUS_MSTOP(5, BIT(12))),
> -       DEF_MOD("wdt_3_clkp",                   CLK_PLLCLN_DIV16, 5, 1, 2, 17,
> -                                               BUS_MSTOP(5, BIT(13))),
> -       DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
> -                                               BUS_MSTOP(5, BIT(13))),
>         DEF_MOD("rtc_0_clk_rtc",                CLK_PLLCM33_DIV16, 5, 3, 2, 19,
>                                                 BUS_MSTOP(3, BIT(11) | BIT(12))),
>         DEF_MOD("rspi_0_pclk",                  CLK_PLLCLN_DIV8, 5, 4, 2, 20,
> @@ -571,10 +559,7 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
>         DEF_RST(7, 2, 3, 3),            /* GTM_5_PRESETZ */
>         DEF_RST(7, 3, 3, 4),            /* GTM_6_PRESETZ */
>         DEF_RST(7, 4, 3, 5),            /* GTM_7_PRESETZ */
> -       DEF_RST(7, 5, 3, 6),            /* WDT_0_RESET */
>         DEF_RST(7, 6, 3, 7),            /* WDT_1_RESET */
> -       DEF_RST(7, 7, 3, 8),            /* WDT_2_RESET */
> -       DEF_RST(7, 8, 3, 9),            /* WDT_3_RESET */
>         DEF_RST(8, 1, 3, 18),           /* RSCI0_PRESETN */
>         DEF_RST(8, 2, 3, 19),           /* RSCI0_TRESETN */
>         DEF_RST(8, 3, 3, 20),           /* RSCI1_PRESETN */
> --
> 2.43.0
>
>