Re: [PATCH v2 1/3] clk: mediatek: add MUX_CLR_SET macro

[Chen-Yu Tsai]

On Thu, Mar 26, 2026 at 1:09 PM Daniel Golle <daniel@xxxxxxxxxxxxxx> wrote:
>
> Some MediaTek SoCs (e.g. MT7988) define infra muxes that have neither
> a clock gate nor an update register.
>
> Add a MUX_CLR_SET convenience macro that takes only the mux register
> offsets, bit shift, and width, hardcoding upd_ofs = 0 and
> upd_shift = -1 so callers cannot accidentally pass bogus sentinel
> values to wrongly-typed fields.
>
> Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx>

Reviewed-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>