RE: [PATCH v2 10/10] arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 26 March 2026 09:40
> Subject: Re: [PATCH v2 10/10] arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface
> 
> Hi Biju,
> 
> On Tue, 3 Feb 2026 at 14:10, Biju <biju.das.au@xxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Enable the Gigabit Ethernet Interface (GBETH1) populated on the RZ/G3L
> > SMARC EVK. Also add pincontrol definitions for GBETH{0,1}.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
> 
> > @@ -53,3 +69,79 @@ phy0: ethernet-phy@7 {
> >                 txd3-skew-psec = <0>;
> >         };
> >  };
> > +
> > +&mdio1 {
> > +       phy1: ethernet-phy@7 {
> > +               compatible = "ethernet-phy-id0022.1640",
> > +                            "ethernet-phy-ieee802.3-c22";
> 
> Drop the latter?

OK.

> 
> > +               reg = <7>;
> > +               rxc-skew-psec = <1400>;
> > +               txc-skew-psec = <1400>;
> > +               rxdv-skew-psec = <0>;
> > +               txdv-skew-psec = <0>;
> 
> txen-skew-psec?

OK.

> 
> > +               rxd0-skew-psec = <0>;
> > +               rxd1-skew-psec = <0>;
> > +               rxd2-skew-psec = <0>;
> > +               rxd3-skew-psec = <0>;
> > +               txd0-skew-psec = <0>;
> > +               txd1-skew-psec = <0>;
> > +               txd2-skew-psec = <0>;
> > +               txd3-skew-psec = <0>;
> > +       };
> > +};
> > +
> > +&pinctrl {
> > +       eth0_pins: eth0 {
> > +               txc {
> > +                       pinmux = <RZG3L_PORT_PINMUX(B, 1, 1)>;  /* ETH0_TXC_REF_CLK */
> > +                       power-source = <1800>;
> > +                       output-enable;
> > +                       drive-strength-microamp = <5200>;
> > +               };
> > +
> > +               ctrl {
> > +                       pinmux = <RZG3L_PORT_PINMUX(A, 1, 1)>, /* MDC */
> > +                                <RZG3L_PORT_PINMUX(A, 0, 1)>, /* MDIO */
> > +                                <RZG3L_PORT_PINMUX(C, 2, 1)>, /* PHY_INTR */
> > +                                <RZG3L_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
> > +                                <RZG3L_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
> > +                                <RZG3L_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
> > +                                <RZG3L_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
> > +                                <RZG3L_PORT_PINMUX(B, 0, 1)>, /* RXC */
> > +                                <RZG3L_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
> > +                                <RZG3L_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
> > +                                <RZG3L_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
> > +                                <RZG3L_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
> > +                                <RZG3L_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
> > +                                <RZG3L_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
> > +                                power-source = <1800>;
> > +               };
> > +       };
> 
> Please spin adding EHT0 pin control off into a separate patch.

OK, will move ETH0 pin control into separate patch.


Cheers,
Biju