Re: [PATCH v8 07/11] clk: renesas: Add support for RZ/G3L SoC

[Geert Uytterhoeven]

On Tue, 24 Mar 2026 at 12:43, Biju <biju.das.au@xxxxxxxxx> wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> The clock structure for RZ/G3L is almost identical to that of the RZ/G3S
> SoC with more IP blocks such as LCDC, CRU, LVDS, and GPU.
>
> Add minimal clock and reset entries required to boot the system on Renesas
> RZ/G3L SMARC EVK and bind it with the RZ/G2L CPG core driver.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v7.1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds