[PATCH 3/7] dt-bindings: clock: qcom: Add Hawi global clock controller
From: Vivek Aknurwar
Date: Mon Mar 30 2026 - 20:41:10 EST
Add device tree bindings for the global clock controller on the Hawi SoC.
Signed-off-by: Vivek Aknurwar <vivek.aknurwar@xxxxxxxxxxxxxxxx>
---
.../devicetree/bindings/clock/qcom,hawi-gcc.yaml | 63 +++++
include/dt-bindings/clock/qcom,hawi-gcc.h | 253 +++++++++++++++++++++
2 files changed, 316 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml
new file mode 100644
index 000000000000..4f428c0f7286
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,hawi-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on Hawi
+
+maintainers:
+ - Vivek Aknurwar <vivek.aknurwar@xxxxxxxxxxxxxxxx>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on Hawi.
+
+ See also: include/dt-bindings/clock/qcom,hawi-gcc.h
+
+properties:
+ compatible:
+ const: qcom,hawi-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board Always On XO source
+ - description: Sleep clock source
+ - description: PCIE 0 Pipe clock source
+ - description: PCIE 1 Pipe clock source
+ - description: UFS PHY RX symbol 0 clock
+ - description: UFS PHY RX symbol 1 clock
+ - description: UFS PHY TX symbol 0 clock
+ - description: USB3 PHY wrapper pipe clock
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,hawi-gcc";
+ reg = <0x00100000 0x1f4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie0_phy>,
+ <&pcie1_phy>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
+ <&usb_1_qmpphy>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,hawi-gcc.h b/include/dt-bindings/clock/qcom,hawi-gcc.h
new file mode 100644
index 000000000000..6cd7fa0884f5
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,hawi-gcc.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_HAWI_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_HAWI_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
+#define GCC_AGGRE_STARDUSTNOC_USB3_PRIM_AXI_CLK 1
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
+#define GCC_BOOT_ROM_AHB_CLK 3
+#define GCC_CAM_BIST_MCLK_AHB_CLK 4
+#define GCC_CAMERA_AHB_CLK 5
+#define GCC_CAMERA_HF_AXI_CLK 6
+#define GCC_CAMERA_RSC_CORE_CLK 7
+#define GCC_CAMERA_SF_AXI_CLK 8
+#define GCC_CAMERA_XO_CLK 9
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11
+#define GCC_CNOC_PCIE_SF_AXI_CLK 12
+#define GCC_EVA_AHB_CLK 13
+#define GCC_EVA_AXI0_CLK 14
+#define GCC_EVA_AXI0C_CLK 15
+#define GCC_EVA_XO_CLK 16
+#define GCC_GP1_CLK 17
+#define GCC_GP1_CLK_SRC 18
+#define GCC_GP2_CLK 19
+#define GCC_GP2_CLK_SRC 20
+#define GCC_GP3_CLK 21
+#define GCC_GP3_CLK_SRC 22
+#define GCC_GPLL0 23
+#define GCC_GPLL0_OUT_EVEN 24
+#define GCC_GPLL4 25
+#define GCC_GPLL5 26
+#define GCC_GPLL7 27
+#define GCC_GPLL9 28
+#define GCC_GPU_CFG_AHB_CLK 29
+#define GCC_GPU_GEMNOC_GFX_CLK 30
+#define GCC_GPU_GPLL0_CLK_SRC 31
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
+#define GCC_GPU_RSC_CORE_CLK 33
+#define GCC_GPU_SMMU_VOTE_CLK 34
+#define GCC_MMU_TCU_VOTE_CLK 35
+#define GCC_PCIE_0_AUX_CLK 36
+#define GCC_PCIE_0_AUX_CLK_SRC 37
+#define GCC_PCIE_0_CFG_AHB_CLK 38
+#define GCC_PCIE_0_MSTR_AXI_CLK 39
+#define GCC_PCIE_0_PHY_AUX_CLK 40
+#define GCC_PCIE_0_PHY_AUX_CLK_SRC 41
+#define GCC_PCIE_0_PHY_RCHNG_CLK 42
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 43
+#define GCC_PCIE_0_PIPE_CLK 44
+#define GCC_PCIE_0_PIPE_CLK_SRC 45
+#define GCC_PCIE_0_PIPE_DIV2_CLK 46
+#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 47
+#define GCC_PCIE_0_SLV_AXI_CLK 48
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49
+#define GCC_PCIE_1_AUX_CLK 50
+#define GCC_PCIE_1_AUX_CLK_SRC 51
+#define GCC_PCIE_1_CFG_AHB_CLK 52
+#define GCC_PCIE_1_MSTR_AXI_CLK 53
+#define GCC_PCIE_1_PHY_AUX_CLK 54
+#define GCC_PCIE_1_PHY_AUX_CLK_SRC 55
+#define GCC_PCIE_1_PHY_RCHNG_CLK 56
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 57
+#define GCC_PCIE_1_PIPE_CLK 58
+#define GCC_PCIE_1_PIPE_CLK_SRC 59
+#define GCC_PCIE_1_PIPE_DIV2_CLK 60
+#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 61
+#define GCC_PCIE_1_RSC_CORE_CLK 62
+#define GCC_PCIE_1_SLV_AXI_CLK 63
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 64
+#define GCC_PCIE_RSC_CORE_CLK 65
+#define GCC_PCIE_RSCC_CFG_AHB_CLK 66
+#define GCC_PCIE_RSCC_XO_CLK 67
+#define GCC_PDM2_CLK 68
+#define GCC_PDM2_CLK_SRC 69
+#define GCC_PDM_AHB_CLK 70
+#define GCC_PDM_XO4_CLK 71
+#define GCC_QUPV3_I2C_CORE_CLK 72
+#define GCC_QUPV3_I2C_S0_CLK 73
+#define GCC_QUPV3_I2C_S0_CLK_SRC 74
+#define GCC_QUPV3_I2C_S1_CLK 75
+#define GCC_QUPV3_I2C_S1_CLK_SRC 76
+#define GCC_QUPV3_I2C_S2_CLK 77
+#define GCC_QUPV3_I2C_S2_CLK_SRC 78
+#define GCC_QUPV3_I2C_S3_CLK 79
+#define GCC_QUPV3_I2C_S3_CLK_SRC 80
+#define GCC_QUPV3_I2C_S4_CLK 81
+#define GCC_QUPV3_I2C_S4_CLK_SRC 82
+#define GCC_QUPV3_I2C_S_AHB_CLK 83
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 84
+#define GCC_QUPV3_WRAP1_CORE_CLK 85
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 86
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 87
+#define GCC_QUPV3_WRAP1_S0_CLK 88
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89
+#define GCC_QUPV3_WRAP1_S1_CLK 90
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91
+#define GCC_QUPV3_WRAP1_S2_CLK 92
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93
+#define GCC_QUPV3_WRAP1_S3_CLK 94
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95
+#define GCC_QUPV3_WRAP1_S4_CLK 96
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97
+#define GCC_QUPV3_WRAP1_S5_CLK 98
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99
+#define GCC_QUPV3_WRAP1_S6_CLK 100
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101
+#define GCC_QUPV3_WRAP1_S7_CLK 102
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK 104
+#define GCC_QUPV3_WRAP2_CORE_CLK 105
+#define GCC_QUPV3_WRAP2_S0_CLK 106
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC 107
+#define GCC_QUPV3_WRAP2_S1_CLK 108
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC 109
+#define GCC_QUPV3_WRAP2_S2_CLK 110
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC 111
+#define GCC_QUPV3_WRAP2_S3_CLK 112
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC 113
+#define GCC_QUPV3_WRAP2_S4_CLK 114
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC 115
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK 116
+#define GCC_QUPV3_WRAP3_CORE_CLK 117
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 118
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 119
+#define GCC_QUPV3_WRAP3_S0_CLK 120
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC 121
+#define GCC_QUPV3_WRAP3_S1_CLK 122
+#define GCC_QUPV3_WRAP3_S1_CLK_SRC 123
+#define GCC_QUPV3_WRAP3_S2_CLK 124
+#define GCC_QUPV3_WRAP3_S2_CLK_SRC 125
+#define GCC_QUPV3_WRAP3_S3_CLK 126
+#define GCC_QUPV3_WRAP3_S3_CLK_SRC 127
+#define GCC_QUPV3_WRAP3_S4_CLK 128
+#define GCC_QUPV3_WRAP3_S4_CLK_SRC 129
+#define GCC_QUPV3_WRAP3_S5_CLK 130
+#define GCC_QUPV3_WRAP3_S5_CLK_SRC 131
+#define GCC_QUPV3_WRAP4_CORE_2X_CLK 132
+#define GCC_QUPV3_WRAP4_CORE_CLK 133
+#define GCC_QUPV3_WRAP4_S0_CLK 134
+#define GCC_QUPV3_WRAP4_S0_CLK_SRC 135
+#define GCC_QUPV3_WRAP4_S1_CLK 136
+#define GCC_QUPV3_WRAP4_S1_CLK_SRC 137
+#define GCC_QUPV3_WRAP4_S2_CLK 138
+#define GCC_QUPV3_WRAP4_S2_CLK_SRC 139
+#define GCC_QUPV3_WRAP4_S3_CLK 140
+#define GCC_QUPV3_WRAP4_S3_CLK_SRC 141
+#define GCC_QUPV3_WRAP4_S4_CLK 142
+#define GCC_QUPV3_WRAP4_S4_CLK_SRC 143
+#define GCC_QUPV3_WRAP_1_M_AXI_CLK 144
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 145
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK 146
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK 147
+#define GCC_QUPV3_WRAP_3_M_AHB_CLK 148
+#define GCC_QUPV3_WRAP_3_S_AHB_CLK 149
+#define GCC_QUPV3_WRAP_4_M_AHB_CLK 150
+#define GCC_QUPV3_WRAP_4_S_AHB_CLK 151
+#define GCC_SDCC2_AHB_CLK 152
+#define GCC_SDCC2_APPS_CLK 153
+#define GCC_SDCC2_APPS_CLK_SRC 154
+#define GCC_SDCC4_AHB_CLK 155
+#define GCC_SDCC4_APPS_CLK 156
+#define GCC_SDCC4_APPS_CLK_SRC 157
+#define GCC_UFS_PHY_AHB_CLK 158
+#define GCC_UFS_PHY_AXI_CLK 159
+#define GCC_UFS_PHY_AXI_CLK_SRC 160
+#define GCC_UFS_PHY_ICE_CORE_CLK 161
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 162
+#define GCC_UFS_PHY_PHY_AUX_CLK 163
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 164
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 165
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 166
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 167
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 168
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 169
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 170
+#define GCC_UFS_PHY_UNIPRO_5_CORE_CLK 171
+#define GCC_UFS_PHY_UNIPRO_5_CORE_CLK_SRC 172
+#define GCC_USB30_PRIM_MASTER_CLK 173
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
+#define GCC_USB30_PRIM_SLEEP_CLK 178
+#define GCC_USB3_PRIM_PHY_AUX_CLK 179
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 180
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 181
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 182
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 183
+#define GCC_VIDEO_AHB_CLK 184
+#define GCC_VIDEO_AXI0_CLK 185
+#define GCC_VIDEO_AXI0C_CLK 186
+#define GCC_VIDEO_XO_CLK 187
+
+/* GCC power domains */
+#define GCC_PCIE_0_GDSC 0
+#define GCC_PCIE_0_PHY_GDSC 1
+#define GCC_PCIE_1_GDSC 2
+#define GCC_PCIE_1_PHY_GDSC 3
+#define GCC_UFS_MEM_PHY_GDSC 4
+#define GCC_UFS_PHY_GDSC 5
+#define GCC_USB30_PRIM_GDSC 6
+#define GCC_USB3_PHY_GDSC 7
+
+/* GCC resets */
+#define GCC_CAMERA_BCR 0
+#define GCC_EVA_AXI0_CLK_ARES 1
+#define GCC_EVA_AXI0C_CLK_ARES 2
+#define GCC_EVA_BCR 3
+#define GCC_GPU_BCR 4
+#define GCC_PCIE_0_BCR 5
+#define GCC_PCIE_0_LINK_DOWN_BCR 6
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 7
+#define GCC_PCIE_0_PHY_BCR 8
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 9
+#define GCC_PCIE_1_BCR 10
+#define GCC_PCIE_1_LINK_DOWN_BCR 11
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 12
+#define GCC_PCIE_1_PHY_BCR 13
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 14
+#define GCC_PCIE_PHY_BCR 15
+#define GCC_PCIE_PHY_CFG_AHB_BCR 16
+#define GCC_PCIE_PHY_COM_BCR 17
+#define GCC_PCIE_RSCC_BCR 18
+#define GCC_PDM_BCR 19
+#define GCC_QUPV3_WRAPPER_1_BCR 20
+#define GCC_QUPV3_WRAPPER_2_BCR 21
+#define GCC_QUPV3_WRAPPER_3_BCR 22
+#define GCC_QUPV3_WRAPPER_4_BCR 23
+#define GCC_QUPV3_WRAPPER_I2C_BCR 24
+#define GCC_QUSB2PHY_PRIM_BCR 25
+#define GCC_QUSB2PHY_SEC_BCR 26
+#define GCC_SDCC2_BCR 27
+#define GCC_SDCC4_BCR 28
+#define GCC_TCSR_PCIE_BCR 29
+#define GCC_UFS_PHY_BCR 30
+#define GCC_USB30_PRIM_BCR 31
+#define GCC_USB3_DP_PHY_PRIM_BCR 32
+#define GCC_USB3_DP_PHY_SEC_BCR 33
+#define GCC_USB3_PHY_PRIM_BCR 34
+#define GCC_USB3_PHY_SEC_BCR 35
+#define GCC_USB3PHY_PHY_PRIM_BCR 36
+#define GCC_USB3PHY_PHY_SEC_BCR 37
+#define GCC_VIDEO_AXI0_CLK_ARES 38
+#define GCC_VIDEO_AXI0C_CLK_ARES 39
+#define GCC_VIDEO_BCR 40
+#define GCC_VIDEO_XO_CLK_ARES 41
+
+#endif
--
2.34.1