Re: [PATCH 2/2] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers

[Conor Dooley]

On Wed, Apr 01, 2026 at 01:12:48AM +0800, Han Gao wrote:
> SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all
> four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent
> so the kernel uses coherent DMA mappings instead of non-coherent bounce
> buffering.

Worth pointing out I guess that this property is needed, despite riscv
being coherent by default, because the whole bus is marked
dma-noncoherent.

> 
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Han Gao <gaohan@xxxxxxxxxxx>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index 9fddf3f0b3b9..3af770549742 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 {
>  			vendor-id = <0x1f1c>;
>  			device-id = <0x2042>;
>  			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>  			msi-parent = <&msi>;
>  			status = "disabled";
>  		};
> @@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 {
>  			vendor-id = <0x1f1c>;
>  			device-id = <0x2042>;
>  			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>  			msi-parent = <&msi>;
>  			status = "disabled";
>  		};
> @@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 {
>  			vendor-id = <0x1f1c>;
>  			device-id = <0x2042>;
>  			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>  			msi-parent = <&msi>;
>  			status = "disabled";
>  		};
> @@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 {
>  			vendor-id = <0x1f1c>;
>  			device-id = <0x2042>;
>  			cdns,no-bar-match-nbits = <48>;
> +			dma-coherent;
>  			msi-parent = <&msi>;
>  			status = "disabled";
>  		};
> -- 
> 2.47.3
>

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