RE: [PATCH 3/3] irqchip/renesas-rzg2l: Add NMI support

[Biju Das]

Hi Thomas,

> -----Original Message-----
> From: Thomas Gleixner <tglx@xxxxxxxxxx>
> Sent: 31 March 2026 21:30
> Subject: RE: [PATCH 3/3] irqchip/renesas-rzg2l: Add NMI support
> 
> On Tue, Mar 31 2026 at 17:10, Biju Das wrote:
> >> From: Thomas Gleixner <tglx@xxxxxxxxxx>
> > Will drop the lock as it is not RMW operation.
> 
> Huch?
> 
> > +static void rzg2l_clear_nmi_int(struct rzg2l_irqc_priv *priv,
> > +unsigned int hwirq) {
> > +	u32 bit = BIT(hwirq);
> > +	u32 reg;
> > +
> > +	reg = readl_relaxed(priv->base + NSCR);
> > +	if (reg & bit) {
> > +		writel_relaxed(reg & ~bit, priv->base + NSCR);
> > +		/*
> > +		 * Enforce that the posted write is flushed to prevent that the
> > +		 * just handled interrupt is raised again.
> > +		 */
> > +		readl_relaxed(priv->base + NSCR);
> > +	}
> > +}
> 
> How is that not RMW?

It is not a shared reg, as there is only a single NMI interrupt and hwirq is always 0.
I will drop BIT(hwirq) to avoid confusion related to the shared register.

> 
> I assume that you want to explain that it's not a RMW on a shared register, right?

Bit16 - NSMON: NMI pin signal level monitor register (read only)
Bit0 - NSTAT: NMI interrupt status. Writing is allowed only when NSTAT is 1.

Yes, I will add a comment: Writing is allowed only when NSTAT is 1.

Cheers,
Biju