Re: MSIs not freed in GICv3 ITS driver

[Manivannan Sadhasivam]

On Mon, Mar 30, 2026 at 09:17:10AM +0100, Marc Zyngier wrote:
> On Tue, 03 Mar 2026 09:26:32 +0000,
> Manivannan Sadhasivam <mani@xxxxxxxxxx> wrote:
> > 
> > The above issue should be applicable to other MSI controller drivers as well,
> > not just DWC.
> 
> The core issue is not with the irqchips, but with the MSI subsystem.
> 
> Multi-MSI devices should always result in a strict power-of-2
> allocation, because that's all the HW supports. Yet, we let drivers
> request a stupid number of interrupts.
> 
> I can see two outcomes: either we force the allocation to the next 2^
> value, or we return an error to the caller. The first one costs memory
> (extra irq descriptors), the latter forces people to fix their crap.
> 
> I'm tempted to propose the latter.
> 

That might cause a lot of regressions I believe. IMO, safe bet would be to
handle the power of 2 allocations inside the irqchip drivers.

- Mani

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