Re: [PATCH v3 15/38] drm/msm/dp: use stream_id to change offsets in dp_catalog

[Dmitry Baryshkov]

On Wed, Apr 01, 2026 at 02:33:49PM +0800, Yongxing Mou wrote:
> 
> 
> On 8/26/2025 2:01 AM, Dmitry Baryshkov wrote:
> > On Mon, Aug 25, 2025 at 10:16:01PM +0800, Yongxing Mou wrote:
> > > From: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
> > > 
> > > Use the dp_panel's stream_id to adjust the offsets for stream 1
> > > which will be used for MST in the dp_catalog. Stream 1 share the
> > > same link clk with stream 0 with different reg offset. Also add
> > 
> > Shares what? How do we handle streams 2 and 3?
> > 
> Stream 0 and stream 1 are controlled by *_DPTX0_LCLK, stream 2 uses
> *_MST_2_LCLK, and stream 3 uses *_MST_3_LCLK. Will update commit message.

So, we might need some better interface for updating those regs.

> > > additional register defines for stream 1.
> > > 
> > > Signed-off-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
> > > Signed-off-by: Yongxing Mou <yongxing.mou@xxxxxxxxxxxxxxxx>
> > > ---
> > >   drivers/gpu/drm/msm/dp/dp_ctrl.c  | 24 ++++++++++---
> > >   drivers/gpu/drm/msm/dp/dp_panel.c | 72 +++++++++++++++++++++++++++------------
> > >   drivers/gpu/drm/msm/dp/dp_reg.h   |  9 +++++
> > >   3 files changed, 79 insertions(+), 26 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
> > > index b851efc132ea03884ce2563990fbc24c9577e724..43a9ce0539906e1f185abf250fdf161e462d9645 100644
> > > --- a/drivers/gpu/drm/msm/dp/dp_reg.h
> > > +++ b/drivers/gpu/drm/msm/dp/dp_reg.h
> > > @@ -141,6 +141,7 @@
> > >   #define DP_STATE_CTRL_PUSH_IDLE			(0x00000100)
> > >   #define REG_DP_CONFIGURATION_CTRL		(0x00000008)
> > > +#define REG_DP1_CONFIGURATION_CTRL		(0x00000400)

I think the file is (mostly) logically sorted. Please don't insert new
entries in the middle of it, breaking the sort order.

> > >   #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK	(0x00000001)
> > >   #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002)
> > >   #define DP_CONFIGURATION_CTRL_P_INTERLACED	(0x00000004)
> > > @@ -159,11 +160,15 @@
> > >   #define REG_DP_SOFTWARE_MVID			(0x00000010)
> > >   #define REG_DP_SOFTWARE_NVID			(0x00000018)
> > >   #define REG_DP_TOTAL_HOR_VER			(0x0000001C)
> > > +#define REG_DP1_SOFTWARE_MVID			(0x00000414)
> > > +#define REG_DP1_SOFTWARE_NVID			(0x00000418)
> > > +#define REG_DP1_TOTAL_HOR_VER			(0x0000041C)
> > >   #define REG_DP_START_HOR_VER_FROM_SYNC		(0x00000020)
> > >   #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY	(0x00000024)
> > >   #define REG_DP_ACTIVE_HOR_VER			(0x00000028)
> > >   #define REG_DP_MISC1_MISC0			(0x0000002C)
> > > +#define REG_DP1_MISC1_MISC0			(0x0000042C)
> > >   #define DP_MISC0_SYNCHRONOUS_CLK		(0x00000001)
> > >   #define DP_MISC0_COLORIMETRY_CFG_SHIFT		(0x00000001)
> > >   #define DP_MISC0_TEST_BITS_DEPTH_SHIFT		(0x00000005)
> > > @@ -230,8 +235,10 @@
> > >   #define MMSS_DP_AUDIO_CTRL_RESET		(0x00000214)
> > >   #define MMSS_DP_SDP_CFG				(0x00000228)
> > > +#define MMSS_DP1_SDP_CFG			(0x000004E0)
> > >   #define GEN0_SDP_EN				(0x00020000)
> > >   #define MMSS_DP_SDP_CFG2			(0x0000022C)
> > > +#define MMSS_DP1_SDP_CFG2			(0x000004E4)
> > >   #define MMSS_DP_AUDIO_TIMESTAMP_0		(0x00000230)
> > >   #define MMSS_DP_AUDIO_TIMESTAMP_1		(0x00000234)
> > >   #define GENERIC0_SDPSIZE_VALID			(0x00010000)
> > > @@ -240,6 +247,7 @@
> > >   #define MMSS_DP_AUDIO_STREAM_1			(0x00000244)
> > >   #define MMSS_DP_SDP_CFG3			(0x0000024c)
> > > +#define MMSS_DP1_SDP_CFG3			(0x000004E8)
> > >   #define UPDATE_SDP				(0x00000001)
> > >   #define MMSS_DP_EXTENSION_0			(0x00000250)
> > > @@ -288,6 +296,7 @@
> > >   #define MMSS_DP_GENERIC1_7			(0x00000344)
> > >   #define MMSS_DP_GENERIC1_8			(0x00000348)
> > >   #define MMSS_DP_GENERIC1_9			(0x0000034C)
> > > +#define MMSS_DP1_GENERIC0_0			(0x00000490)
> > >   #define MMSS_DP_VSCEXT_0			(0x000002D0)
> > >   #define MMSS_DP_VSCEXT_1			(0x000002D4)
> > > 
> > > -- 
> > > 2.34.1
> > > 
> > 
> 

-- 
With best wishes
Dmitry