Re: MSIs not freed in GICv3 ITS driver

[Manivannan Sadhasivam]

On Wed, Apr 01, 2026 at 09:15:30AM +0100, Marc Zyngier wrote:
> On Wed, 01 Apr 2026 08:59:02 +0100,
> Manivannan Sadhasivam <mani@xxxxxxxxxx> wrote:
> > 
> > On Mon, Mar 30, 2026 at 09:17:10AM +0100, Marc Zyngier wrote:
> > > On Tue, 03 Mar 2026 09:26:32 +0000,
> > > Manivannan Sadhasivam <mani@xxxxxxxxxx> wrote:
> > > > 
> > > > The above issue should be applicable to other MSI controller drivers as well,
> > > > not just DWC.
> > > 
> > > The core issue is not with the irqchips, but with the MSI subsystem.
> > > 
> > > Multi-MSI devices should always result in a strict power-of-2
> > > allocation, because that's all the HW supports. Yet, we let drivers
> > > request a stupid number of interrupts.
> > > 
> > > I can see two outcomes: either we force the allocation to the next 2^
> > > value, or we return an error to the caller. The first one costs memory
> > > (extra irq descriptors), the latter forces people to fix their crap.
> > > 
> > > I'm tempted to propose the latter.
> > > 
> > 
> > That might cause a lot of regressions I believe. IMO, safe bet would be to
> > handle the power of 2 allocations inside the irqchip drivers.
> 
> What part of "this is a violation of the PCI spec" did you miss? I
> didn't realise we were in the business of adding crap just because
> endpoint drivers are broken.
> 

I agree that the endpoint drivers requesting non power-of-2 MSIs is flawed in
the first place. But a lot of drivers do:

pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_INTX);
or
pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);

This is so far working for these drivers and *may* suddenly break if the irqchip
drivers start returning errors. I was just trying to avoid that situation.

> In any case, I'm not touching the ITS driver.
> 

Sure. You are the maintainer, so its your call end of the day.

- Mani

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