Re: [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Chen Wang]

On 3/27/2026 4:19 PM, Yao Zi wrote:
> On Thu, Mar 26, 2026 at 10:15:16PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Feb 27, 2026 at 06:19:25PM +0000, Yao Zi wrote:
> > > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > > states for devicetree platforms") force enable ASPM on all device tree
> > > platform, the SG2042 root port breaks as it advertises L0s and L1
> > > capabilities without supporting it.
> > >
> > > Provide a platform-specific initialization hook to override the L0s and
> > > L1 support advertised in LNKCAP register of SG2042 Root Ports, so it
> > > doesn't try to enable those states.
> > >
> > > Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> > > Co-authored-by: Inochi Amaoto <inochiama@xxxxxxxxx>
> > > Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxx>
> > > Signed-off-by: Yao Zi <me@xxxxxxxx>
> > > ---
> > >   drivers/pci/controller/cadence/pcie-sg2042.c | 20 ++++++++++++++++++++
> > >   1 file changed, 20 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
> > > index 0c50c74d03ee..3142f82bd393 100644
> > > --- a/drivers/pci/controller/cadence/pcie-sg2042.c
> > > +++ b/drivers/pci/controller/cadence/pcie-sg2042.c
> > > @@ -32,6 +32,25 @@ static struct pci_ops sg2042_pcie_child_ops = {
> > >   	.write		= pci_generic_config_write,
> > >   };
> > >   
> > > +static int sg2042_pcie_disable_l0s_l1(struct cdns_pcie_rc *rc)
> > > +{
> > > +	struct cdns_pcie *pcie = &rc->pcie;
> > > +	u32 pcie_lnkcap_off;
> > > +	u32 lnkcap;
> > > +
> > > +	pcie_lnkcap_off = CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP;
> > > +
> > > +	lnkcap = cdns_pcie_rp_readw(pcie, pcie_lnkcap_off);
> > > +	lnkcap &= ~PCI_EXP_LNKCAP_ASPMS;
> > > +	cdns_pcie_rp_writew(pcie, pcie_lnkcap_off, lnkcap);
> > > +
> > cadence-host driver already has cdns_pcie_host_init_root_port() to initialize
> > the Root Port. Since your intention is to modify the LNKCAP field, which belongs
> > to the Root Port, you should do that in cdns_pcie_host_init_root_port() instead.
> > I see no sg2042 specific registers used in this patch, so just set a flag in
> > this driver like 'broken_aspm' and clear PCI_EXP_LNKCAP_ASPMS if set in
> > cdns_pcie_host_init_root_port().
> Okay, it makes sense. Will do it in v3.

Keep it up, Yao :) I'm looking forward to your v3!

Chen

> > - Mani
> >
> > --
> > மணிவண்ணன் சதாசிவம்
> Regards,
> Yao Zi