Re: [PATCH v1 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT

[Conor Dooley]

On Thu, Apr 02, 2026 at 01:40:19AM -0700, Changhuang Liang wrote:
> From: Ley Foon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx>
> 
> Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT, PLIC,
> PMU, UART and 1GB DDR.
> 
> Signed-off-by: Ley Foon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx>
> Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
> ---
>  MAINTAINERS                                   |   6 +
>  arch/riscv/boot/dts/starfive/Makefile         |   2 +
>  .../boot/dts/starfive/jhb100-evb1-eth.dts     |   6 +
>  arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi |  32 ++
>  arch/riscv/boot/dts/starfive/jhb100.dtsi      | 326 ++++++++++++++++++
>  5 files changed, 372 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
>  create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
>  create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7d10988cbc62..b1892a480c31 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -25306,6 +25306,12 @@ S:	Supported
>  F:	Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
>  F:	drivers/irqchip/irq-starfive-jh8100-intc.c
>  
> +STARFIVE JHB100 DEVICETREES
> +M:	Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
> +L:	linux-riscv@xxxxxxxxxxxxxxxxxxx
> +S:	Maintained

Supported, no?

> +F:	arch/riscv/boot/dts/starfive/jhb100*
> +
>  STATIC BRANCH/CALL
>  M:	Peter Zijlstra <peterz@xxxxxxxxxxxxx>
>  M:	Josh Poimboeuf <jpoimboe@xxxxxxxxxx>
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 3dd1f05283f7..7cdb75788053 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> +
> +dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1-eth.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> new file mode 100644
> index 000000000000..62cd046e1224
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> + */
> +
> +#include "jhb100-evb1.dtsi"

What is the point of this file? Is this the base-board?
Shouldn't it have a specific compatible?

Can the SoM be used without a base board? I've got no info about this
board appearing on google, do you even have pictures of it or any
documentation?
I see this
https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=22
and
https://www.starfivetech.com/en/index.php?s=hardware&c=show&id=23
but the former doesn't look like it needs a base-board and the latter is
called "evb3", so is not what's here?

Not got enough info to really do any kind of review here.

> diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> new file mode 100644
> index 000000000000..462b6fb7953b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> + */
> +
> +#include "jhb100.dtsi"
> +
> +/ {
> +	model = "StarFive JHB100 EVB-1";
> +	compatible = "starfive,jhb100-evb1", "starfive,jhb100";
> +
> +	aliases {
> +		serial6 = &uart6;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial6:115200n8";
> +	};
> +
> +	cpus {
> +		timebase-frequency = <5000000>;
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x40000000 0x0 0x40000000>;	/* 1GB */
> +	};
> +};
> +
> +&uart6 {
> +	status = "okay";
> +};

> +		cpu2: cpu@2 {
> +			compatible = "starfive,dubhe-70", "riscv";
> +			riscv,isa = "rv64imafdcbh";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
> +					       "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
> +					       "zicond", "zicsr", "zifencei", "zihintpause",
> +					       "zihpm", "svinval", "svnapot", "sscofpmf";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			d-cache-block-size = <64>;
> +			d-cache-sets = <512>;
> +			d-cache-size = <32768>;
> +			d-tlb-sets = <1>;
> +			d-tlb-size = <16>;
> +			device_type = "cpu";
> +			i-cache-block-size = <64>;
> +			i-cache-sets = <512>;
> +			i-cache-size = <32768>;
> +			i-tlb-sets = <1>;
> +			i-tlb-size = <24>;
> +			mmu-type = "riscv,sv48";
> +			next-level-cache = <&l2c2>;
> +			reg = <0x2>;

reg after compatible please.

> +			tlb-split;
> +
> +			cpu2_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};

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