linux-next: manual merge of the amdgpu tree with the drm-next tree

[Mark Brown]

Hi all,

Today's linux-next merge of the amdgpu tree got a conflict in:

  drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

between commit:

  86117c5ab42f2 ("drm/amd/display: Fix NULL pointer dereference in dcn401_init_hw()")

from the drm-next tree and commit:

  e927b36ae18b6 ("drm/amd/display: Fix NULL pointer dereference in dcn401_init_hw()")

from the amdgpu tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --combined drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 53d70db372a97,7e6bdefb5471e..0000000000000
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@@ -140,7 -140,7 +140,7 @@@ void dcn401_init_hw(struct dc *dc
  	struct dc_bios *dcb = dc->ctx->dc_bios;
  	struct resource_pool *res_pool = dc->res_pool;
  	int i;
- 	int edp_num;
+ 	unsigned int edp_num;
  	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
  	uint32_t user_level = MAX_BACKLIGHT_LEVEL;
  	bool dchub_ref_freq_changed;
@@@ -368,20 -368,19 +368,19 @@@
  		    dc->res_pool->funcs->update_bw_bounding_box &&
  		    dc->clk_mgr && dc->clk_mgr->bw_params) {
  			/* update bounding box if FAMS2 disabled, or if dchub clk has changed */
 -			if (dc->clk_mgr)
 -				dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 +			dc->res_pool->funcs->update_bw_bounding_box(dc,
 +								    dc->clk_mgr->bw_params);
  		}
  	}
  }
  
- void dcn401_trigger_3dlut_dma_load(struct pipe_ctx *pipe_ctx)
+ void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)
  {
- 	const struct pipe_ctx *primary_dpp_pipe_ctx = resource_get_primary_dpp_pipe(pipe_ctx);
- 	struct hubp *primary_hubp = primary_dpp_pipe_ctx ?
- 			primary_dpp_pipe_ctx->plane_res.hubp : NULL;
+ 	(void)dc;
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
  
- 	if (primary_hubp && primary_hubp->funcs->hubp_enable_3dlut_fl) {
- 		primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true);
+ 	if (hubp->funcs->hubp_enable_3dlut_fl) {
+ 		hubp->funcs->hubp_enable_3dlut_fl(hubp, true);
  	}
  }
  
@@@ -389,11 -388,8 +388,8 @@@ bool dcn401_set_mcm_luts(struct pipe_ct
  				const struct dc_plane_state *plane_state)
  {
  	struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc;
- 	const struct pipe_ctx *primary_dpp_pipe_ctx = resource_get_primary_dpp_pipe(pipe_ctx);
  	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
  	struct hubp *hubp = pipe_ctx->plane_res.hubp;
- 	struct hubp *primary_hubp =	primary_dpp_pipe_ctx ?
- 			primary_dpp_pipe_ctx->plane_res.hubp : NULL;
  	const struct dc_plane_cm *cm = &plane_state->cm;
  	int mpcc_id = hubp->inst;
  	struct mpc *mpc = dc->res_pool->mpc;
@@@ -491,41 -487,25 +487,25 @@@
  			mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, 12, mpcc_id);
  
  		if (mpc->funcs->update_3dlut_fast_load_select)
- 			mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, primary_hubp->inst);
+ 			mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);
  
  		/* HUBP */
- 		if (primary_hubp->inst == hubp->inst) {
- 			/* only program if this is the primary dpp pipe for the given plane */
- 			if (hubp->funcs->hubp_program_3dlut_fl_config)
- 				hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma);
+ 		if (hubp->funcs->hubp_program_3dlut_fl_config)
+ 			hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma);
  
- 			if (hubp->funcs->hubp_program_3dlut_fl_crossbar)
- 				hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, cm->lut3d_dma.format);
+ 		if (hubp->funcs->hubp_program_3dlut_fl_crossbar)
+ 			hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, cm->lut3d_dma.format);
  
- 			if (hubp->funcs->hubp_program_3dlut_fl_addr)
- 				hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr);
+ 		if (hubp->funcs->hubp_program_3dlut_fl_addr)
+ 			hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr);
  
- 			if (hubp->funcs->hubp_enable_3dlut_fl) {
- 				hubp->funcs->hubp_enable_3dlut_fl(hubp, true);
- 			} else {
- 				/* GPU memory only supports fast load path */
- 				BREAK_TO_DEBUGGER();
- 				lut_enable = false;
- 				result = false;
- 			}
+ 		if (hubp->funcs->hubp_enable_3dlut_fl) {
+ 			hubp->funcs->hubp_enable_3dlut_fl(hubp, true);
  		} else {
- 			/* re-trigger priamry HUBP to load 3DLUT */
- 			if (primary_hubp->funcs->hubp_enable_3dlut_fl) {
- 				primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true);
- 			}
- 
- 			/* clear FL setup on this pipe's HUBP */
- 			memset(&lut3d_dma, 0, sizeof(lut3d_dma));
- 			if (hubp->funcs->hubp_program_3dlut_fl_config)
- 				hubp->funcs->hubp_program_3dlut_fl_config(hubp, &lut3d_dma);
- 
- 			if (hubp->funcs->hubp_enable_3dlut_fl)
- 				hubp->funcs->hubp_enable_3dlut_fl(hubp, false);
+ 			/* GPU memory only supports fast load path */
+ 			BREAK_TO_DEBUGGER();
+ 			lut_enable = false;
+ 			result = false;
  		}
  	} else {
  		/* Legacy (Host) Load Mode */
@@@ -577,6 -557,7 +557,7 @@@ bool dcn401_set_output_transfer_func(st
  				struct pipe_ctx *pipe_ctx,
  				const struct dc_stream_state *stream)
  {
+ 	(void)dc;
  	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
  	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
  	const struct pwl_params *params = NULL;
@@@ -638,6 -619,7 +619,7 @@@ static void enable_stream_timing_calc
  		struct drr_params *params,
  		unsigned int *event_triggers)
  {
+ 	(void)dc;
  	struct dc_stream_state *stream = pipe_ctx->stream;
  	int i;
  
@@@ -1415,6 -1397,7 +1397,7 @@@ void dcn401_dmub_hw_control_lock(struc
  		struct dc_state *context,
  		bool lock)
  {
+ 	(void)context;
  	/* use always for now */
  	union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
  
@@@ -1835,41 -1818,42 +1818,42 @@@ void dcn401_perform_3dlut_wa_unlock(str
  	 * This is meant to work around a known HW issue where VREADY will cancel the pending 3DLUT_ENABLE signal regardless
  	 * of whether OTG lock is currently being held or not.
  	 */
- 	const struct pipe_ctx *otg_master_pipe_ctx = resource_get_otg_master(pipe_ctx);
- 	struct timing_generator *tg = otg_master_pipe_ctx ?
- 			otg_master_pipe_ctx->stream_res.tg : NULL;
- 	const struct pipe_ctx *primary_dpp_pipe_ctx = resource_is_pipe_type(pipe_ctx, DPP_PIPE) ?
- 			resource_get_primary_dpp_pipe(pipe_ctx) : pipe_ctx;
- 	struct hubp *primary_hubp = primary_dpp_pipe_ctx ?
- 			primary_dpp_pipe_ctx->plane_res.hubp : NULL;
+ 	struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL };
+ 	struct pipe_ctx *odm_pipe, *mpc_pipe;
+ 	int i, wa_pipe_ct = 0;
  
- 	if (!otg_master_pipe_ctx && !tg) {
- 		return;
+ 	for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) {
+ 		for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe->bottom_pipe) {
+ 			if (mpc_pipe->plane_state &&
+ 					mpc_pipe->plane_state->cm.flags.bits.lut3d_enable &&
+ 					mpc_pipe->plane_state->cm.flags.bits.lut3d_dma_enable) {
+ 				wa_pipes[wa_pipe_ct++] = mpc_pipe;
+ 			}
+ 		}
  	}
  
- 	if (primary_dpp_pipe_ctx &&
- 			primary_dpp_pipe_ctx->plane_state &&
- 			primary_dpp_pipe_ctx->plane_state->cm.flags.bits.lut3d_enable &&
- 			primary_dpp_pipe_ctx->plane_state->cm.flags.bits.lut3d_dma_enable) {
- 		if (tg->funcs->set_vupdate_keepout)
- 			tg->funcs->set_vupdate_keepout(tg, true);
+ 	if (wa_pipe_ct > 0) {
+ 		if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)
+ 			pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, true);
  
- 		if (primary_hubp->funcs->hubp_enable_3dlut_fl) {
- 			primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true);
+ 		for (i = 0; i < wa_pipe_ct; ++i) {
+ 			if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)
+ 				wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);
  		}
  
- 		tg->funcs->unlock(tg);
- 		if (tg->funcs->wait_update_lock_status)
- 			tg->funcs->wait_update_lock_status(tg, false);
+ 		pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
+ 		if (pipe_ctx->stream_res.tg->funcs->wait_update_lock_status)
+ 			pipe_ctx->stream_res.tg->funcs->wait_update_lock_status(pipe_ctx->stream_res.tg, false);
  
- 		if (primary_hubp->funcs->hubp_enable_3dlut_fl) {
- 			primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true);
+ 		for (i = 0; i < wa_pipe_ct; ++i) {
+ 			if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)
+ 				wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);
  		}
  
- 		if (tg->funcs->set_vupdate_keepout)
- 			tg->funcs->set_vupdate_keepout(tg, false);
+ 		if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)
+ 			pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, false);
  	} else {
- 		tg->funcs->unlock(tg);
+ 		pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
  	}
  }
  
@@@ -1888,6 -1872,7 +1872,7 @@@ void dcn401_reset_back_end_for_pipe
  		struct pipe_ctx *pipe_ctx,
  		struct dc_state *context)
  {
+ 	(void)context;
  	struct dc_link *link = pipe_ctx->stream->link;
  	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
  
@@@ -1943,7 -1928,7 +1928,7 @@@
  		 * the case where the same symclk is shared across multiple otg
  		 * instances
  		 */
- 		if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+ 		if (dc_is_tmds_signal(pipe_ctx->stream->signal))
  			link->phy_state.symclk_ref_cnts.otg = 0;
  		if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
  			link_hwss->disable_link_output(link,
@@@ -3263,6 -3248,7 +3248,7 @@@ void dcn401_update_writeback_sequence
  		struct dc_state *context,
  		struct block_sequence_state *seq_state)
  {
+ 	(void)context;
  	struct dwbc *dwb;
  	struct mcif_wb *mcif_wb;
  
@@@ -3468,6 -3454,7 +3454,7 @@@ void dcn401_enable_plane_sequence(struc
  				 struct dc_state *context,
  				 struct block_sequence_state *seq_state)
  {
+ 	(void)context;
  	struct dce_hwseq *hws = dc->hwseq;
  	uint32_t org_ip_request_cntl = 0;

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