[PATCH v1 0/5] Initial device tree support for StarFive JHB100 SoC

[Changhuang Liang]

StarFive JHB100 SoC consists of 4 RISC-V low power Cores (Dubhe-70). It
also features various interfaces such as I2C, SPI, CAN, USB, MMC, Uart,
etc.

This patch series introduces initial SoC DTSI support for the StarFive
JHB100 SoC. The relevant dt-binding documentation has been updated
accordingly. Below is the list of IP blocks added in the initial SoC DTSI.

- StarFive Dubhe-70 CPU
- PMU
- PLIC
- CLINT
- UART

This patch series is based on tag 7.0-rc5 and has been tested on the
StarFive JHB100 EVB-1.

Ji Sheng Teoh (1):
  dt-bindings: riscv: Add StarFive Dubhe-70 compatibles

Ley Foon Tan (4):
  dt-bindings: timer: Add StarFive JHB100 clint
  dt-bindings: interrupt-controller: Add StarFive JHB100 plic
  dt-bindings: riscv: Add StarFive JHB100 SoC
  riscv: dts: starfive: jhb100: Add JHB100 base DT

 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/cpus.yaml       |   1 +
 .../devicetree/bindings/riscv/starfive.yaml   |   5 +
 .../bindings/timer/sifive,clint.yaml          |   1 +
 MAINTAINERS                                   |   6 +
 arch/riscv/boot/dts/starfive/Makefile         |   2 +
 .../boot/dts/starfive/jhb100-evb1-eth.dts     |   6 +
 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi |  32 ++
 arch/riscv/boot/dts/starfive/jhb100.dtsi      | 326 ++++++++++++++++++
 9 files changed, 380 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi


base-commit: c369299895a591d96745d6492d4888259b004a9e
prerequisite-patch-id: 5735e71493da6858decc510a0e75967744b66b39
--
2.25.1