Re: [PATCh v3 04/14] ASoC: rsnd: Add RZ/G3E SoC probing and register map

[Mark Brown]

On Thu, Apr 02, 2026 at 06:24:26PM +0200, John Madieu wrote:

> @@ -629,7 +632,9 @@ struct rsnd_priv {
>  #define RSND_GEN4	(4 << 0)
>  #define RSND_SOC_MASK	(0xFF << 4)
>  #define RSND_SOC_E	(1 << 4) /* E1/E2/E3 */
> -
> +#define RSND_RZ_MASK	(0xFF << 8)

This overlaps with RSND_SOC_MASK.  That might be intentional but I'm
really not sure and it's all kind of unclear.

> +#define RSND_RZ3	(3 << 8)
> +#define RSND_RZG3E	(1 << 12)

These are both in RSND_RZ_MASK but use different absolute shifts which
makes it less than obvious.  It looks like the lower nibble of the mask
is the number from the revision and the upper is the letter?

It might help to use GENMASK() and FIELD_PREP() for this stuff, and to
refactor the defines to use subfields.  Like I say it's all a bit hard
to follow.

Attachment: signature.asc
Description: PGP signature