Re: [PATCH 5/6] drm/msm/adreno: add Adreno 810 GPU support

[Alexander Koskovich]

On Wednesday, April 1st, 2026 at 6:15 AM, Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx> wrote:

> 
> I may be on an older tag or something, but:
> 
> $ diff /tmp/downstream.txt /tmp/upstream.txt
> 24a25
> > { GEN7_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
> 27,28c28,29
> < { GEN8_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) },
> < { GEN8_UCHE_MODE_CNTL, 0x00020000, BIT(PIPE_NONE) },
> ---
> > { GEN8_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) },
> > { GEN8_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
> 31,32c32
> < /* Disable write slow pointer in data phase queue */
> < { GEN8_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) },
> ---
> > { GEN8_UCHE_CACHE_WAYS, 0x00080000, BIT(PIPE_NONE) },
> 
> 
> > +};
> > +
> > +static const u32 a810_protect_regs[] = {
> 
> $ diff /tmp/downstream.txt /tmp/upstream.txt
> 
> < A6XX_PROTECT_NORDWR(0x0ae00, 0x0),
> < A6XX_PROTECT_NORDWR(0x0ae02, 0x4),
> ---
> > A6XX_PROTECT_NORDWR(0x0ae00, 0x6),
> 
> -> the difference is that
> 
> SP_DBG_ECO_CNTL and SP_ADDR_MODE_CNTL are not protected
> 
> that might have been a part of the ^ difference

Going back for v2 and making sure this is 1:1 to GRAPHICS.LA.14.0.r5-03100-lanai.0, I
think I was going back and forth between my own downstream from the OEM,
GRAPHICS.LA.14.0.r5 and GRAPHICS.LA.15.0.r1.

GRAPHICS.LA.15.0.r1 has gen8_3_0 support, but I'm not sure if there are any
devices that actually ship with it on that branch. Seemed to be fairly out
of sync from LA.14.

> 
> Also it may be that the better name for this table is a830_protect_regs[]

Can you elaborate on this? The only names I know this GPU by are "a810" and
"gen8_3_0".

> 
> 
> The other tables, I'm lost. Akhil, please take a look.
> 
> 
> Konrad

Thanks,
Alex
> 
>