Re: [PATCh v3 07/14] ASoC: rsnd: ssui: Add RZ/G3E SSIU BUSIF support

[Kuninori Morimoto]

Hi John

Thank you for your patch

> Add support for the SSIU found on the Renesas RZ/G3E SoC, which
> provides a different BUSIF layout compared to earlier generations:
> 
>  - SSI0-SSI4: 4 BUSIF instances each (BUSIF0-3)
>  - SSI5-SSI8: 1 BUSIF instance each (BUSIF0 only)
>  - SSI9: 4 BUSIF instances (BUSIF0-3)
>  - Total: 28 BUSIFs
> 
> RZ/G3E also differs from Gen2/Gen3 implementations in that only two
> pairs of BUSIF error-status registers are available instead of four,
> and the SSI always operates in BUSIF mode with no PIO fallback.
> 
> Rather than scattering SoC-specific checks across functional code,
> introduce an extra capability flags in the match data:
> 
>  - RSND_SSIU_BUSIF_STATUS_COUNT_2: only two BUSIF error-status
>    register pairs are present. Used in rsnd_ssiu_busif_err_irq_ctrl()
>    and rsnd_ssiu_busif_err_status_clear() to limit register iteration.
> 
> Future SoCs sharing these constraints can set the flags without
> requiring code changes.
> 
> Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
> ---
(snip)
> @@ -72,7 +73,7 @@ static void rsnd_ssiu_busif_err_irq_ctrl(struct rsnd_mod *mod, int enable)
>  		return;
>  	}
>  
> -	for (i = 0; i < 4; i++) {
> +	for (unsigned int i = 0; i < priv->ssiu_busif_count; i++) {
>  		enum rsnd_reg reg = SSI_SYS_INT_ENABLE((i * 2) + offset);
>  		u32 val = 0xf << (shift * 4);
>  		u32 sys_int_enable = rsnd_mod_read(mod, reg);
(snip)
> @@ -109,7 +110,7 @@ bool rsnd_ssiu_busif_err_status_clear(struct rsnd_mod *mod)
>  		goto out;
>  	}
>  
> -	for (i = 0; i < 4; i++) {
> +	for (unsigned int i = 0; i < priv->ssiu_busif_count; i++) {
>  		u32 reg = SSI_SYS_STATUS(i * 2) + offset;
>  		u32 status = rsnd_mod_read(mod, reg);
>  		u32 val = 0xf << (shift * 4);

ssiu_busif_count is for SSIU specific, no need to have it on priv.
Please move it on rsnd_ssiu.

Thank you for your help !!

Best regards
---
Kuninori Morimoto