[GIT PULL] MIPS fixes for v7.0
From: Thomas Bogendoerfer
Date: Sun Apr 05 2026 - 05:42:50 EST
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/ tags/mips-fixes_7.0_1
for you to fetch changes up to 01cc50ea5167bb14117257ec084637abe9e5f691:
mips: mm: Allocate tlb_vpn array atomically (2026-04-01 22:24:36 +0200)
----------------------------------------------------------------
Fix TLB uniquification for systems with TLB not initialised by firmware
Fix allocation in TLB uniquification
Fix SiByte cache initialisation
Check uart parameters from firmware on Loongson64 systems
Fix clock id mismatch for Ralink SoCs
Fix GCC version check for __mutli3 workaround
----------------------------------------------------------------
Maciej W. Rozycki (5):
MIPS: SiByte: Bring back cache initialisation
MIPS: Fix the GCC version check for `__multi3' workaround
MIPS: Always record SEGBITS in cpu_data.vmbits
MIPS: mm: Suppress TLB uniquification on EHINV hardware
MIPS: mm: Rewrite TLB uniquification for the hidden bit feature
Rong Zhang (1):
MIPS: Loongson64: env: Check UARTs passed by LEFI cautiously
Shiji Yang (1):
mips: ralink: update CPU clock index
Stefan Wiehler (1):
mips: mm: Allocate tlb_vpn array atomically
arch/mips/include/asm/cpu-features.h | 1 -
arch/mips/include/asm/cpu-info.h | 2 -
arch/mips/include/asm/mipsregs.h | 2 +
arch/mips/kernel/cpu-probe.c | 13 +-
arch/mips/kernel/cpu-r3k-probe.c | 2 +
arch/mips/lib/multi3.c | 6 +-
arch/mips/loongson64/env.c | 18 ++-
arch/mips/mm/cache.c | 3 +-
arch/mips/mm/tlb-r4k.c | 285 ++++++++++++++++++++++++++++-------
arch/mips/ralink/clk.c | 8 +-
10 files changed, 268 insertions(+), 72 deletions(-)
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