[GIT PULL] RISC-V devicetrees for v7.1

[Conor Dooley]

Hey folks,

Realised as I was tagging this that the tsu clock and gpio interrupts
changes miss the pic64gx and should have been rebased. I'll send another
PR later this week I think, with those two fixes. Nothing is broken by
the two fixes, they just didn't fix the newly added dts, which is why I
still feel comfortable sending this, particularly given I am pretty late
already. My excuse is that I was sick all last week...

Cheers,
Conor.

The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:

  Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-dt-for-v7.1

for you to fetch changes up to b0258f69f1e0ed98e8506706da9ef538389b27ea:

  riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC (2026-03-31 15:51:52 +0100)

----------------------------------------------------------------
RISC-V devicetrees for v7.1

Generic:
Add binding coverage for Supm.

Microchip:
Add support for the picgx64 and its curiosity board. This is a PolarFire
SoC without the FPGA.
Add the missing tsu_clk for ptp on the macb on PolarFire SoC and resolve
a long-running problem with gpio interrupts being incorrectly described
on the platform.

Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>

----------------------------------------------------------------
Conor Dooley (3):
      riscv: dts: microchip: add pinctrl nodes for mpfs/icicle kit
      riscv: dts: microchip: add tsu clock to macb on mpfs
      riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC

Guodong Xu (1):
      dt-bindings: riscv: Add Supm extension description

Pierre-Henry Moussay (4):
      dt-bindings: timer: sifive,clint: add pic64gx compatibility
      dt-bindings: riscv: microchip: document the PIC64GX curiosity kit
      riscv: dts: microchip: add pic64gx and its curiosity kit
      riscv: dts: microchip: remove POLARFIRE mention in Makefile

 .../devicetree/bindings/riscv/extensions.yaml      |  27 +
 .../devicetree/bindings/riscv/microchip.yaml       |   7 +-
 .../devicetree/bindings/timer/sifive,clint.yaml    |   1 +
 arch/riscv/boot/dts/microchip/Makefile             |  17 +-
 .../riscv/boot/dts/microchip/mpfs-beaglev-fire.dts |  29 +
 arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts   |  43 +-
 .../boot/dts/microchip/mpfs-icicle-kit-common.dtsi |  38 +-
 .../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi |  63 +++
 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts  |  41 +-
 arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi    | 167 ++++++
 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts  |  29 +
 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts     |  37 +-
 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts     |  35 +-
 arch/riscv/boot/dts/microchip/mpfs.dtsi            |  59 +-
 .../boot/dts/microchip/pic64gx-curiosity-kit.dts   | 165 ++++++
 arch/riscv/boot/dts/microchip/pic64gx-pinctrl.dtsi | 177 ++++++
 arch/riscv/boot/dts/microchip/pic64gx.dtsi         | 630 +++++++++++++++++++++
 17 files changed, 1499 insertions(+), 66 deletions(-)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
 create mode 100644 arch/riscv/boot/dts/microchip/pic64gx-pinctrl.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/pic64gx.dtsi

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