[PATCH 0/5] clk: qcom: Fix RCG/branch MND divider and timeout issues

[Xilin Wu]

This series fixes several bugs in the Qualcomm clock RCG and branch
drivers that surface when clocks are used at low frequencies or with
the MND duty cycle control path (clk_rcg2_gp_ops).

Patches 1-2 fix the GP clock MND divider computation
(clk_rcg2_calc_mnd) and the duty cycle setting path
(clk_rcg2_set_duty_cycle). The calc_mnd function has u16 overflow
issues and incorrect n_max/pre_div calculations that produce wrong
frequencies. The set_duty_cycle function has a u32 overflow that
produces wrong duty cycles when n is large.

Patches 3-4 replace the fixed polling timeouts in clk_branch_wait()
and update_config() with dynamically computed values based on the
configured clock rate. The existing fixed timeouts (200 us / 500 us)
are too short for clocks running at low rates (tens of Hz to low kHz),
causing spurious timeout warnings and clock configuration failures.

Patch 5 fixes an integer truncation bug in the duty cycle boundary
checks that allows out-of-range values to be written to the D
register, causing RCG configuration update failures.

These bugs do not affect clocks using the standard clk_rcg2_ops with
pre-defined frequency tables, but they are triggered when GP clocks
are used with clk_rcg2_gp_ops for PWM-style output at arbitrary
frequencies and duty cycles.

Signed-off-by: Xilin Wu <sophon@xxxxxxxxx>
---
Xilin Wu (5):
      clk: qcom: clk-rcg2: fix clk_rcg2_calc_mnd() producing wrong M/N/pre_div
      clk: qcom: clk-rcg2: use 64-bit arithmetic in set_duty_cycle()
      clk: qcom: clk-branch: calculate timeout based on clock frequency
      clk: qcom: clk-rcg2: calculate timeout based on clock frequency
      clk: qcom: clk-rcg2: fix set_duty_cycle() integer overflow in boundary checks

 drivers/clk/qcom/clk-branch.c | 22 ++++++++++++++++--
 drivers/clk/qcom/clk-rcg.h    |  2 ++
 drivers/clk/qcom/clk-rcg2.c   | 53 ++++++++++++++++++++++++++++++++++---------
 3 files changed, 64 insertions(+), 13 deletions(-)
---
base-commit: 2febe6e6ee6e34c7754eff3c4d81aa7b0dcb7979
change-id: 20260406-clk-qcom-gpclk-fixes-fde4e81a00d2

Best regards,
--  
Xilin Wu <sophon@xxxxxxxxx>